臺灣博碩士論文加值系統

對於傳統的金氧半場效電晶體(MOSFETs)而言，次臨界擺幅(Subthreshold Swing)的物理限制無法再降低，使得電晶體元件的臨界電壓與功率耗損，無法隨元件微縮而下降。穿隧電晶體(Tunnel Field-Effect Transistors, TFETs)因利用閘極偏壓控制能帶間穿隧(Band-to-Band Tunneling)來進行元件操作，使其電晶體元件的次臨界擺幅，能突破傳統金氧半電晶體下限，成為未來極具潛力的綠能電晶體元件架構。本論文藉由二維元件模擬及適當的物理模型與參數，探討新穎穿隧電晶體之相關元件設計及發展解析的穿隧電晶體物理模型。
由於操作電流及短通道效應在同質接面或陡異質接面的穿隧電晶體中面臨限制，因此，於此論文中，提出一種新穎的漸變異質接面(Graded Heterojunction)通道結構，以提昇穿隧電晶體的操作電流，並改善穿隧電晶體的通道微縮性。操作電流在陡異質接面穿隧電晶體中的降低，肇因於陡接面的能帶差所造成的熱載子放射，藉由採用漸變異質接面結構於穿隧電晶體中，能消除相關現象，縮短穿隧距離，有效提高操作電流。而採用漸變異質接面通道結構的穿隧電晶體，其能帶結構可正確調整，使得穿隧能障的高度與寬度皆能被閘極偏壓有效地控制，使通道長度微縮至10奈米以下時，穿隧電晶體仍能維持理想的次臨界擺幅。於此論文中，針對漸變異質接面的相關元件參數，如汲極的摻雜及異質漸變度，亦進行深入的探討，以將此漸變異質接面穿隧電晶體的操作電流、開關特性及漏電流最佳化。對於次十奈米的短通道漸變異質接面的穿隧電晶體而言，中度摻雜的汲極及純鍺的源極，能將此綠能元件的特性最佳化，裨益於低功率及高密度積體電路的未來應用。
結合低能障隙半導體(Low-Bandgap Semiconductors)材料於線穿隧電晶體(Line-Tunneling TFETs)中，能有效提升穿隧電晶體的操作電流並同時具有低次臨界擺幅的開關特性。於此論文中，深入探討局部區域與非局部電場(Local and Nonlocal Electric Fields)在穿隧過程中之影響，以正確地瞭解於低能障隙半導體其能帶間穿隧效應的物理機制。對於具有較高能隙的半導體材料而言，與穿隧機率相關的非局部電場，在穿隧過程中具有主導的地位；而局部電場與入射穿隧電子數量相關，其在低能隙半導體材料中扮演重要角色。藉由以局部與非局部電場在穿隧發生率(Tunneling Generation Rate)解析式的分離表示方法，此論文正確地解析敘述低能障隙半導體其能帶間穿隧效應的物理機制。利用此一新穿隧發生率解析方法，發展可用於低能隙半導體的線穿隧電晶體之穿隧電流物理模型，並對相關的元件設計與穿隧機制深入探討。透過最短穿隧路徑(Minimum Tunnel Path)的描述，穿隧電晶體的電流能以清晰易懂的解析式加以表示，作為有用的元件設計準則。而線穿隧電晶體的源極摻雜濃度與閘氧層厚度這兩項主要的設計參數，也分別以數學解析及數值模擬方式加以驗證討論，研究結果顯示穿隧電晶體的最短穿隧路徑值可作為其元件特性的有效參考指標。

The insurmountable limit of 60 mV/decade subthreshold swing at room temperature in traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) leads to the non-scalability of the threshold voltage and associated power consumption. Based on the gate-controlled band-to-band tunneling, tunnel field-effect transistors (TFETs) have demonstrated to overcome the MOSFET’s swing limit to serve as a promising candidate for energy-efficient applications. Using two-dimensional simulations with appropriate models and parameters, this dissertation explores the design and modeling of the advanced TFET devices to elucidate the physical mechanism, to optimize the operating characteristic, and to extend the potential scalability.
Owing to the limitations of homojunction and abrupt heterojunction structures in on-current and short-channel effect, a new graded heterojunction approach is proposed to significantly boost the on-current and to further scale down the channel lengths of TFETs. The lowering of on-current observed in abrupt heterojunction TFETs is physically attributed to the thermal emission barriers formed by abrupt energy-band offsets. By employing graded heterojunctions, the thermal emission barriers for electrons/holes are completely eliminated to narrow the tunnel-barrier widths for enhancing the TFET current. With the bandgap engineering of graded heterojunctions, both the height and width of the tunnel barrier are highly controlled by applying gate voltages to ensure a nearly ideal switching of scaled sub-10 nm TFETs. Critical device factors, such as the drain profile and bandgap engineering, are examined to generate favorable characteristics in the on-current, on-off switching, and off-leakage of the very short TFETs. A mildly doped drain with a pure Ge source is preferred in designing the short-channel graded TFETs for low-power and high-packing-density integrated circuits.
Using low bandgap semiconductors in line-tunneling TFETs has demonstrated an excellent combination to simultaneously maximize the on-current and minimize the subthreshold swing. To better understand the physical principle of band-to-band tunneling in low bandgap semiconductors, the physical properties as well as the roles of local and nonlocal electric fields in tunneling processes are elucidated in this thesis. While the nonlocal field related to the tunneling probability dominates in high bandgap materials, the local field associated with the number of incident tunneling electrons plays a more important role in low bandgap semiconductors. Based on the new expression of tunneling generation rate reformulated by decoupling the local and nonlocal fields, this work elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. The TFET current is derived in term of the minimum tunnel path with friendly analytical forms for practical use. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.

Table of Contents
Acknowledgements i
論文摘要 iii
Abstract v
Table of Contents vii
List of Figures x
List of Tables xvi
Chapter 1 : Introduction 1
1.1 Transistors for Low Power Applications 1
1.2 Subthreshold Swing Limit of Traditional MOSFETs 2
1.3 TFETs with Sub-60 mV/decade Subthreshold Swing 3
1.4 Challenges of TFET Devices 4
1.5 Thesis Objective and Organization 5
Chapter 2 : Overview of Band-to-Band Tunneling Theories 9
2.1 WKB Approximation 9
2.2 Two-Band Kane Models 11
2.3 BTBT Generation Rates 14
2.3.1 Density of states 14
2.3.2 Velocity in k-space 15
2.3.3 Incident electron flux 15
2.3.4 Transmission factors 16
2.3.5 Tunneling rates 17
2.4 TCAD Simulation Models 18
Chapter 3 : TFET Operation and Model Verification 22
3.1 On-Off Switching Mechanism 22
3.2 Temperature-Independent Subthreshold Swing 23
3.3 Calculation and Verification of Model Parameters 24
3.3.1 Indirect bandgap semiconductors 25
3.3.2 Direct bandgap semiconductors 27
Chapter 4 : Enhancing On-Current of TFETs 40
4.1 Homojunction TFETs 40
4.2 Weakness of Abrupt Heterojunction 42
4.3 Graded Heterojunction Approach 46
Chapter 5 : High TFET Scalability with Advanced Techniques 61
5.1 Drain Engineering 61
5.1.1 Design of drain in extremely-scaled TFETs 62
5.1.2 SiGe source heterojunctions 66
5.2 Graded Si/Ge Heterojunction 67
5.2.1 Bandgap engineering 69
5.2.2 Scaling into sub-10 nm regimes 70
5.3 Design of Graded Si/SiGe TFETs 71
5.3.1 Ge composition in graded heterojunctions 72
5.3.2 Role of drain in graded TFETs 74
Chapter 6 : Modeling and Design of Low-Bandgap Line-Tunneling TFETs 98
6.1 Physics of BTBT in Low Bandgap Semiconductors 99
6.1.1 Tunneling properties 99
6.1.2 Roles of local and nonlocal fields 101
6.2 Applying Low Bandgap Semiconductors in Line-Tunneling TFETs 104
6.3 Modeling and Design of Low-Bandgap Line-Tunneling TFETs 106
6.3.1 Analytical line-tunneling TFET models 107
6.3.2 Design considerations 111
Chapter 7 : Conclusions 129
Appendix: Publications 132
References 134

References
[1] “ICT statistics,” International Telecommunication Union, 2014.
[2] W.-Y. Lu and Y. Taur, “On the scaling limit of ultrathin SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1137-1141, May 2006.
[3] D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, A.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. of the IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
[4] B. J. Lin, “Lithography till the end of Moore’s law,” in Proceedings of the 2012 ACM International Symposium on Physical Design, 2012, pp. 1-2.
[5] B. L. Anderson and R. L. Anderson, “Fundamentals of Semiconductor Devices,” McGraw-Hill, 2005, p. 445.
[6] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743-745, Aug. 2007.
[7] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature,” IEEE Electron Device Lett., vol. 32, no. 4, pp. 437-439, Apr. 2011.
[8] R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤50-mV/decade subthreshold swing,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1504-1506, Nov. 2011.
[9] T. Krishnamohan, K. Donghyun, S. Raghunathan, and K. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60mV/dec subthreshold slope,” in IEDM Tech. Dig., 2008, pp. 1-3.
[10] S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, “Germanium-source tunnel field effect transistors with record high ION/IOFF,” in VLSI Symp. Tech. Dig., 2009, pp. 178–179.
[11] C. L. Royer, A. Villalon, D. Cooper, F. Andrieu, J.-M. Hartmann, P. Perreau, and B. Prévitali, “High performance FDSOI MOSFETs and TFETs using SiGe channels and raised source and drain,” in Proceedings of the International Silicon-Germanium Technology and Device Meeting (ISTDM), 2012, pp. 1-2.
[12] Y. Liu, H.-J. Wang, J. Yan, and G.-Q. Han, “A silicon tunnel field-effect transistor with an in situ doped single crystalline Ge source for achieving sub-60 mV/decade subthreshold swing,” Chin. Phys. Lett., vol. 30, no. 8, pp. 088502-088502-3, Jun. 2013.
[13] D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu, D. Loubychev, J. Fastenau, and S. Datta, “Experimental staggered-source and N+ pocket-doped Channel III–V tunnel field-effect transistors and their scalabilities,” Appl. Phys. Exp., vol. 4,pp. 024105-024105-3, Feb. 2011.
[14] G. Dewey, B. Chu-Kung, J. Boardman, J. M. Fastenau, J. Kavalieros, R. Kotlyar, W. K. Liu, D. Lubyshev, M. Metz, N. Mukherjee, P. Oakey, R. Pillarisetty, M. Radosavljevic, H. W. Then, and R. Chau, “Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing,” in IEDM Tech. Dig., 2011, pp. 785-788.
[15] J. Appenzeller, Y.-M. Lin , J. Knoch , and Ph. Avouris, “Band-to-band tunneling in carbon nanotube field-effect transistors,” Phys. Rev. Lett., vol. 93, no. 19, pp. 196905-196805-4, Nov. 2004.
[16] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 1725-1733, Jul. 2007.
[17] C. Anghel, P. Chilagani, A. Amara, and A. Vladimirescu, “Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric,” Appl. Phys. Lett., Vol. 96, no. 12, pp. 122104-122104-3, Mar. 2010.
[18] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications,” J. Appl. Phys., vol. 103, no. 10, p. 104504, May 2008.
[19] Q. Zhang, W. Zhao, and S. A. Seabaugh, “Low-subthreshold swing tunnel transistors,” IEEE Electron Device Lett., vol. 27, no. 4, pp. 297-300, Apr. 2006.
[20] A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, “Tunnel field-effect transistor without gate-drain overlap,” Appl. Phys. Lett., vol. 91, no. 5, p. 053102, Jul. 2007.
[21] A. Chattopadhyay and A. Mallik, “Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistor,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 677-683, Mar. 2011.
[22] N. Cui, R. Liang, J. Xu, “Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation,” Appl. Phys. Lett., vol. 98, no. 14, pp. 142105-142105-3, Apr. 2011.
[23] H. G. Virani, S. Gundapaneni, and A. Kottantharayil, “Double dielectric spacer for the enhancement of silicon p-channel tunnel field effect transistor performance,” Jpn. J. Appl. Phys., vol. 50, pp. 04DC04-04DC04-6, Apr. 2011.
[24] G. Lee, J.-S. Jang, and W. Y. Choi, “Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors,” Semicond. Sci. Technol., vol. 28, pp. 052001-052001-5, 2013.
[25] K. L. Low, C. Zhan, G. Han, Y. Yang, K.-H. Goh, P. Guo, E.-H. Toh, and Y.-C. Yeo, “Device physics and design of a L-shaped germanium source tunneling transistor,” Jpn. J. Appl. Phys., vol. 51, pp. 02BC04-02BC04-6, Feb. 2012.
[26] W. Wang, P.-F. Wang, C.-M. Zhang, X. Lin, X.-Y. Liu, Q.-Q. Sun, P. Zhou, and D. W. Zhang, “Design of U-shape channel tunnel FETs with SiGe source regions,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 193-197, Jan. 2014.
[27] B. Ghosh and M. W. Akram, “Junctionless tunnel field effect transistor,” IEEE Electron Device Lett., vol . 34, no. 5, pp. 584-586, May 2013.
[28] K. K. Bhuwalka, J. Schulze, and I. Eisele, “A simulation approach to optimize the electrical parameters of a vertical tunnel FET,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1541-1547, Jul. 2005.
[29] Boucart and A. M. Ionescu, “Length scaling of the double gate tunnel FET with a high-k gate dielectric,” Solid-State Electron., vol. 51, no. 11-12, pp. 1500-1507, Nov.-Dec. 2007.
[30] K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer,” Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073-4078, Jul. 2004.
[31] P.-F. Wang, K. Hilsenbeck, Th. Nirschl, M. Oswald, Ch. Stepper, M. Weis, D. Schmitt-Landsiedel, and W. Hansch, “Complementary tunneling transistor for low power application,” Solid-State Electron., vol. 48, pp. 2281-2286, May 2004.
[32] L. Liu, D. Mohata, and S. Datta, “Scaling length theory of double-gate interband tunnel field-effect transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 902-908, Apr. 2012.
[33] W. G. Vandenberghe, A. S. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, “Analytical model for a tunnel field-effect transistor,” in Proceedings of IEEE Mediterranean Electrotechnical Conference (MELECON), 2008, pp. 923-928.
[34] A. S. Verhulst, D. Leonelli, R. Rooyackers, and G. Groeseneken, “Drain voltage dependent analytical model of tunnel field-effect transistors,” J. Appl. Phys., vol. 110, no. 2, p. 024510, Jul. 2011.
[35] N. Cui, L. Liu, Q. Xie, Z. Tan, R. Liang, J. Wang, and J. Xu, “A two-dimensional analytical model for tunnel field effect transistor and its applications,” Jpn. J. Appl. Phys., vol. 52, no. 4, p. 044303, Apr. 2013.
[36] C. Zener, “A theory of the electrical breakdown of solid dielectrics,” in Proc. R. Soc. Lond. A, vol. 145, no. 855, pp. 523-529, Jul. 1934.
[37] L. Esaki, “New phenomenon in narrow germanium p-n junctions,” Phys. Rev., vol. 109, no. 2, pp. 603-604, Jan. 1958.
[38] L. Keldysh, “Behavior of non-metallic crystals in strong electric fields,” Sov. Phys. JETP, vol. 6, no. 4, pp. 763- 770, Apr. 1958.
[39] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solids, vol. 12, no. 2, pp. 181-188, Jan. 1960.
[40] G. A. M. Hurkx, “On the modelling of tunnelling currents in reverse-biased p-n junctions,” Solid-State Electron., vol. 32, no. 8, pp. 665-668, Aug. 1989.
[41] G. A. M. Hurkx, “A New recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331-338, Sep. 2009.
[42] A. Schenk, “Rigorous theory and simplified model of the band-to-band tunneling in silicon,” Solid-State Electron., vol. 36, no. 1, pp. 19-34, May 1993.
[43] S. Tanaka, “A unified theory of direct and indirect interband tunneling under a nonuniform electric field,” Solid-State Electron., vol. 37, no. 8, pp. 1543-1552, Oct. 1994.
[44] M. Luisier and G. Klimeck, “Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling,” J. Appl. Phys., vol. 107, no. 8, pp. 084507-084507-6, Apr. 2010.
[45] W. Vandenberghe, B. Sorée, W. Magnus, and M. V. Fischetti, “Generalized phonon-assisted Zener tunneling in indirect semiconductors with non-uniform electric fields: A rigorous approach,” J. Appl. Phys., vol. 109, no. 8, pp. 124503-124503-12, Jun. 2011.
[46] M. Oehme, M. Sarlija, D. Hahnel, M. Kaschel, J. Werner, E. Kasper, and J Schulze, “Very high room-temperature peak-to-valley current ratio in Si Esaki tunneling diodes (March 2010),” IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2857-2863, Nov. 2010.
[47] T. Baba, “Proposal for surface tunnel transistors,” Jpn. J. Appl. Phys., vol. 31, no. 4B, pp. L455-L457, Apr. 1992.
[48] D. J. Griffiths, “Introduction to Quantum Mechanics,” Prentice Hall, New Jersey, 1994, pp. 274-297.
[49] S. M. Sze, “Physics of Semiconductor Devices,” 2nd edition, Wiley, New York, 1981.
[50] J. L. Moll, “Physics of Semiconductors,” McGraw-Hill, New York, 1970, p. 252.
[51] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 31, no. 1, pp. 83-91, 1961.
[52] K. Leo, “High-field transport in semiconductor superlattices,” Springer, 2003, pp. 1-8.
[53] B. K. Ridley, “Quantum Processes in Semiconductors,” Oxford University Press, 1999, pp. 44-81.
[54] W. M. Reddick and G. A. J. Amaratunga, “Silicon surface tunneling transistor,” Appl. Phys. Lett., vol. 67, no. 4, pp. 494-496, May 1995.
[55] O. M. Nayfeh, J. L. Hoyt, D. A. Antoniadis, “Strained-Si1-xGex/Si band-to-band tunneling transistors: Impact of tunnel junction germanium composition and doping concentration on switching behavior,” IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2264-2269, Sep. 2009.
[56] K.-H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Sorée, G. Groeseneken, and K. D. Meyer, “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 292-301, Feb. 2012.
[57] J. Z. Peng, S. Haddad, J. Hsu, J. Chen, S. Longcor, and C. Chang, “Accurate simulation on band-to-band tunneling induced leakage current using a global non-local model,” in Proceedings of International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 1995, p. 141.
[58] W.-Y. Loh, K. Jeon, C. Y. Kang, J. Oh, T.-J. K. Liu, H. H. Tseng, W. Xiong, P. Majhi, R. Jammy, and C. Hu, “Highly scaled (Lg 56 nm) gate-last Si tunnel field-effect transistors with ION 100 μA/μm,” Solid-State Electron., vol. 65-66, pp. 22-27, Nov.-Dec. 2011.
[59] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2010.
[60] D. Leonelli, A. Vandooren, R. Rooyackers, A. S. Verhulst, S. D. Gendt, M. M. Heyns, and G. Groeseneken, “Silicide engineering to boost Si tunnel transistor drive current,” Jpn. J. Appl. Phys., vol. 50, no. 4, pp. 04DC05-04DC05-4, Apr. 2011.
[61] A. Vandooren, D. Leonelli, R. Rooyackers, A. Hikavyy, K. Devriendt, M. Demand, R. Loo, G. Groeseneken, and C. Huyghebaert “Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs,” Solid-State Electron., vol. 83, pp. 50-55, 2013.
[62] G. B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Can interface traps suppress TFET ambipolarity?” IEEE Electron Device Lett., vol. 34, no. 12, pp. 1557-1559, Dec. 2013.
[63] A. C. Ford, C. W. Yeung, S. Chuang, H. S. Kim, E. Plis, S. Krishna, C. Hu, and A. Javey, “Ultrathin body InAs tunneling field-effect transistors on Si substrates”, Appl. Phys. Lett., vol. 98, no. 11, p. 113105, Mar. 2011.
[64] T. Krishnamohan, D. Kim, C. D. Nguyen, C. Jungemann, Y. Nishi, and K. C. Saraswat, “High-mobility low band-to-band-tunneling strained-germanium double-gate heterostructure FETs: Simulations,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1000-1009, May 2006.
[65] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, no. 4, pp. 2234-2252, Aug. 1996.
[66] M. E. Levinshtein, S. L. Rumyantsev, and M. S. Shur, “Properties of Advanced Semiconductor Materials: GaN, AlN, InN, BN, SiC, SiGe,” New York: Wiley, 2001.
[67] C. Rivas, R. Lake, G. Klimeck, W. R. Frensley, M. V. Fischetti, P. E. Thompson, S. L. Rommel, and P. R. Berger, “Full-band simulation of indirect phonon-assisted tunneling in a silicon tunnel diode with delta-doped contacts,” Appl. Phys. Lett., vol. 78, no. 6, pp. 814-816, Feb. 2001.
[68] M. V. Fischetti, T. P. O’ Regan, S. Narayanan, C. Sachs, S. Jin, J. Kim, and Y. Zhang, “Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10-nm gate-length,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2116-2136, Sep. 2007.
[69] R. A. Logan, J. M. Rowell, and F. A. Trumbore, “Phonon spectra of Ge-Si alloys,” Phys. Rev., vol. 136, no. 6A, pp. 1751-1755, Dec. 1964.
[70] A. G. Chynoweth, R. A. Logan, and D. E. Thomas, “Phonon-assisted tunneling in silicon and germanium Esaki junctions,” Phys. Rev., vol. 125, no. 3, pp. 877-881, Feb. 1962.
[71] J.-L. Ma, H.-M. Zhang, X.-Y. Wang, Q. Wei, G.-Y. Wang, and X.-B. Xu, “Valence band structure and hole effecitve mass of uniaxial stressed germanium,” J. Comput. Electron., vol. 10, no. 4, pp. 388-393, Oct. 2011.
[72] X. Wang, D. L. Kencke, K. C. Liu, L. F. Register, and S. K. Banerjee, “Band alignments in sidewall strained Si/strained SiGe heterostructures,” Solid-State Electron., vol. 46, no. 12, pp. 2021-2025, Dec. 2002.
[73] A. Rahman, M. S. Lundstrom, and A. W. Ghosh, “Generalized effective-mass approach for n-type metal-oxide-semiconductor field-effect transistors on arbitrarily oriented wafers,” J. Appl. Phys., vol. 97, no. 5, pp. 053702-053702-12, 2005.
[74] S. J. Koester, I. Lauer, A. Majumdar, J. Cai, J. Sleight, S. Bedell, P. Solomon, S. Laux, L. Chang, S. Koswatta, W. Haensch, P. Tomasini, and S. Thomas, “Are Si-SiGe tunneling field-effect transistors a good idea?” ECS Trans., vol. 33, no. 6, pp. 357-361, 2010.
[75] D. K. Mohata, R. Bijesh, V.Saripalli, T. Mayer, and S. Datta, “Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor,” in Proceedings of Device Research Conference (DRC), 2011, pp. 203-204.
[76] D. Pawlik, B. Romanczyk, P. Thomas, S. Rommel, M. Edirisooriya, R. Contreras-Guerrero, R. Droopad, W.-Y. Loh, M. H. Wong, K. Majumdar, W.-E Wang, P. D. Kirsch, and R. Jammy, “Benchmarking and improving III-V Esaki diode performance with a record 2.2 MA/cm2 peak current density to enhance TFET drive current,” in IEDM Tech. Dig., 2012, pp. 812-814.
[77] J.-Y. Li and J. C. Sturm, “The effect of germanium fraction on high-field band-to-band tunneling SiGe junctions in forward and reverse biases,” IEEE Trans. Electron Devices, vol. 60, no. 8, pp. 2479-2484, Aug. 2013.
[78] X. Guo and E. F. Schubert, “Current crowding and optical saturation effects in GaInN/GaN light-emitting diodes grown on insulating substrates,” Appl. Phys. Lett., vol. 78, no. 21, pp. 3337–3339, May 2001.
[79] S. Mookerjea and S. Datta, “Comparative study of Si, Ge and InAs based steep subthreshold slope tunnel transistors for 0.25V supply voltage logic applications”, in Tech. Dig. of the 66th Device Research Conference, 2008, pp. 47-48.
[80] S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta, “Temperature dependent I–V characteristics of a vertical In0.53Ga0.47As tunnel FET,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 564-566, Jun. 2010.
[81] H. G. Virani, R. B. Rao, and A. Kottantharayil, “Investigation of novel Si/SiGe heterostructures and gate induced source tunneling for improvement of p-channel tunnel field-effect transistors”, Jpn. J. Appl. Phys., vol. 49, No. 4, pp. 04DC12-04DC12-5, Apr. 2010.
[82] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, “Device design and scalability of a double-gate tunneling field-effect transistor with silicon–germanium source,” Jpn. J. Appl. Phys., vol. 47, no. 4, pp. 2593-2597, Apr. 2008.
[83] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, “Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization,” Appl. Phys. Lett., vol. 90, no. 26, pp. 263507-263507-3, Jun. 2007.
[84] E.-H. Toh, G.-H. Wang, and Y.-C. Yeo, “Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction,” Appl. Phys. Lett., vol. 91, no. 24, pp. 243505-243505-3, Dec. 2007.
[85] International Technology Roadmap for Semiconductor, 2013 edition.
[86] Y. Khatami and K. Banerjee, “Scaling analysis of graphene nanoribbon tunnel-FETs,” in Device Research Conference (DRC), 2009, pp. 197-198.
[87] M. G. Bardon, H. P. Neves, R. Puers, and C. V. Hoof, “Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions,” IEEE Trans. Electron Devices, vol. 57, pp. 827-834, Apr. 2010.
[88] Y. Taur, C. H. Wann, and D. J. Frank, “25 nm CMOS design considerations,” in IEDM Tech. Dig., 1998, pp. 789-792.
[89] Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752-2761, Nov. 2009.
[90] P.-F. Wang, T. Nirschl, D. Schmitt-Landsiedel, W. Hansch, “Simulation of the Esaki-tunneling FET,” Solid-State Electron., vol. 47, no.7, pp. 1187-1192, Jul. 2003.
[91] C. Hu, “Green transistor as a solution to the IC power crisis,” in 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2008, pp. 16-20.
[92] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329-337, Nov. 2011.
[93] A. C. Seabaugh and Q. Zhang, “Low voltage tunnel transistors for beyond CMOS logic,” Proceedings of the IEEE, vol. 98, pp. 2095-2110, Dec. 2010.
[94] M. Luisier and G. Klimeck, “Performance comparisons of tunneling field-effect transistors made of InSb, carbon, and GaSb-InAs broken gap heterostructures,” in IEDM Tech. Dig., 2009, pp. 913-916.
[95] M. S. Tyagi, “Determination of effective mass and the pair production energy for electrons in germanium from Zener diode characteristics,” Jpn. J. Appl. Phys., vol. 12, no. 1, pp. 106-108, Jan. 1973.
[96] A. S. Verhulst, B. Soree, D. Leonelli, W. G. Vandenberghe, and G. Groeseneken, “Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor,” J. Appl. Phys., vol. 107, no. 2, 024518, Jan. 2010.
[97] W. G. Vandenberghe, A. S. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, “Analytical model for point and line tunneling in a tunnel field-effect transistor,” in Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2008, pp. 137-140.
[98] D. Verreck, A. S. Verhulst, K.-H. Kao, W. G. Vandenberghe, K. D. Meyer, and G. Groeseneken, “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2128-2134, Jul. 2013.
[99] K.-H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Soree, W. Magnus, D. Leonelli, G. Groeseneken, and K. D. Meyer, “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2070-2077, Aug. 2012.
[100] C.-H. Shih and J.-S. Wang, “Threshold voltage of ultrathin gate-insulator MOSFETs,” IEEE Electron Device Lett., vol. 30, no. 3, pp. 278-281, Mar. 2009.
[101] W. Lee and W. Y. Choi, “Influence of inversion layer on tunneling field-effect transistors,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1191-1193, Sep. 2011.