臺灣博碩士論文加值系統

本論文提出了一個採用隨機取樣突波抑制技術的3GHz低突波、低抖動之全數位式鎖相迴路。由於輸入參考頻率以及Bang-Bang相位偵測器的非線性特性，會造成輸出頻譜上會有突波的發生，造成電磁干擾等等問題，因此我們提出了一個隨機取樣突波抑制技術，在不破壞整體迴路穩定性的情形下，去打散輸入參考頻率所造成的固定周期性行為。此外，由於此全數位鎖相迴路將應用於數位電路系統的時脈產生器上，低抖動也是我們設計此電路所必須達到的要求之一。為了達到低抖動以及低突波，整個迴路會由一個鎖定控制器(Locking controller)去控制，在不同的鎖定階段採取不同的迴路濾波器的參數，來達到比較好的效能。
此外，我們採用了一個差動式多相位且具有50%責任週期(Duty Cycle)的數位控制環式振盪器，並利用單一尺寸的變容器(unary varactor)，來達到非常好的線性度。而多相位的輸出可供傳輸端及接收端平行取樣使用。最後整體晶片的設計皆利用台積電的標準元件資料庫(Standard Cell Library)，因此可以簡短設計流程所需時間以及容易在不同製程上實現。
此論文中的晶片是使用台積電40nm 1P9M CMOS製程實現，經模擬結果顯示，在鎖定後所產生的輸出時脈信號為8個相位、頻率為3GHz的時脈信號，其週期抖動(period jitter)的均方根植為0.92ps (0.28%UI)，峰對峰值為5.68ps (1.70%UI)，參考頻率突波為-52.91dBc。整體晶片的核心電路面積分別為數位控制電路:0.0245mm2和數位控制震盪器: 0.0075mm2，在使用正常電壓0.9V下，功率消耗為12.18mW (4.06mW/GHz).

A 3GHz low spur and low jitter all-digital phase-locked loop with random-sampling spur suppression technique has been designed and implemented. Due to the periodic behavior caused by input reference frequency and limit cycle presented in the Bang-Bang phase detector, there are some unwanted spurious tones appear in the output spectrum. The spurious energy must be as low as possible to prevent some unwanted electromagnetic interference (EMI) problem. Thus, we propose a random-sampling spur suppression technique to solve this spurious problem without sacrificing the loop stability. Besides, jitter performance is a very important design consideration because of application for clock source in the digital circuit.
Governed by a locking controller to adjust the loop parameter during different locking stages, we can achieve better jitter and spur performance. Besides, we realize a multi-phase differential digitally-controlled ring-based oscillator. It can generate multi-phase clock signal with nearly 50% duty cycle for parallel sampling in the multiplexed transceiver. By utilizing unary varactor as the capacitive loading, the tuning curve shows good linearity. In this proposed all-digital phase-locked loop, all the logic cells are from standard cell library, so it can be called “fully all-digital phase-locked loop”. Therefore, the design can be easily ported to other CMOS technology process due to the cell-based nature.
This chip is implemented with the TSMC 40nm 1P9M CMOS general purpose process. The post-layout simulations show that the ADPLL can generate 8 multi-phase 3GHz clock signals. The RMS and peak-to-peak period jitter are 0.92ps (0.28%UI) and 5.68ps (1.70%UI), respectively. The reference spur level is -52.91dBc. The core area of digital controller circuit and digitally-controlled oscillator are 0.0245mm2 and 0.0075mm2, respectively. The power consumption is 12.18mW (4.06mW/GHz) when supply voltage is 0.9V.

Chapter 1 Introduction 1
1.1 Motivation 1
1.1.1 Introduction of ADPLL 1
1.1.2 Target Application and Spurious Problem 3
1.2 Thesis Organization 3
Chapter 2 Overview of ADPLL 5
2.1 Architecture of ADPLL 5
2.2 Analysis of Timing Jitter and Frequency Spectrum 7
2.2.1 Timing Jitter 7
2.2.2 Spectrum and Phase noise 11
2.2.3 Relationship between Jitter and Phase noise 14
2.3 State-of-the-Art of ADPLL 16
Chapter 3 Proposed Spur Suppression ADPLL 18
3.1 Block Diagram of the ADPLL 18
3.2 Frequency acquisition stage 21
3.3 Phase tracking stage and Dithering stage 24
3.4 Random-Sampling Technique for Spur-Reduction 30
3.4.1 Random Number Generator 40
3.4.2 Multi-Phase Generator 41
3.5 Digitally-Controlled Oscillator 43
3.5.1 DCO Resolution 44
3.5.2 Delay Cell 45
3.5.3 Dithering Technique 49
3.6 Digital Loop Filter &; Locking Controller 51
3.7 Summary 51
Chapter 4 Chip Design and Implementation 53
4.1 Digital Controller Implementation 53
4.2 DCO Implementation 54
4.3 Full-Chip Implementation of the Proposed ADPLL 61
Chapter 5 Conclusion and Future Works 67
5.1 Conclusion 67
5.2 Future Work 68
Reference 70

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