臺灣博碩士論文加值系統

由於靜態隨機存取記憶體的高運算速度和高性能，近年來已被廣泛用於許多電子產品中。此外，靜態隨機存取記憶體也已廣泛應用於高性能微處理器的高速緩存區和嵌入式系統。因為高速度與面積考量，標準6T 靜態隨機存取記憶體單元一直以來都是主流。在先進技術中，標準6T 靜態隨機存取記憶體因為製程的變異所以寫入能力嚴重退化。特別是，在低的操作電壓，6T SRAM單元幾乎沒有辦法正常操作。
對於低功耗的應用，本文提出一個256 Kb 6T 靜態隨機存取記憶體並具備電源控制和低擺幅感測。電源控制減少了在待機狀態下的漏電功耗。低擺幅的感測在1.1V操作時降低了15％的功耗。為了提高寫入的能力，我們提出了VTRIP寫入輔助和負電壓輔助架構。透過聯電40奈米CMOS低功耗製程，此論文寫作之6T靜態隨機存取記憶體組成之256Kb晶片且面積是308x522 微米平方。該晶片具有非常寬的電壓操作範圍從1.5V到0.6V，工作頻率為800MHz@1.1V和25℃。在1.1V與溫度為25度C時，其待機功率為5.7微瓦。另外在電路操作時，讀取所耗的功率為1057微瓦，而寫入所耗的功率為793微瓦。

SRAMs have been widely used for most of electronic products due to their high operation speed and high performance in recent years. Moreover, SRAMs have been applied to the high-performance microprocessor cache and embedded system. Standard 6T SRAM cell becomes the mainstream of SRAMs design due to its highest speed and compact area. In advanced technology node, write-ability suffers a serious degradation by process variation [1]. Especially, at low operation voltage, 6T SRAM cell almost couldn’t have normal operation.
For low-power, this thesis presents a 256-Kb 6T SRAM with Power-Gating scheme and Low-Swing Sensing. Power-Gating scheme reduces the leakage power during standby. The Low-Swing sensing decreases 15% reading power @1.1V per operation. To enhance the Write-ability, Vtrip Write Assist and Negative–Power-Assist are employed. The 308 x 522um2 256-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology. The chip has wide voltage range from 1.5V to 0.6V, with operating frequency of 800MHz@1.1V and 25℃. The standby power is 5.7uW @1.1V and 25℃. For the dynamic power, the read power is 1049uW and the write power is 793uW @1.1V and 25℃.

Chapter 1 Introduction …...…………………………………………………… 1
1.1 Motivation and Goals ....…………………………………………… 1
1.2 Thesis Organization .……………………………………………..… 2
Chapter 2 Overview of 6T SRAM Design ……………………………………. 3
2.1 The 6T SRAM ………………..……………………………………. 3
2.1.1 Structure of 6T SRAM …………………………….…….……. 3
2.1.2 Hold Static Noise Margin ………………….…………………. 4
2.1.3 Read Static Noise Margin …………………….………………. 5
2.1.4 Write Static Noise Margin ……………………………………. 6
2.1.5 Write Margin …………………………………………………. 7
2.1.6 Read Disturbance and Half Selected Disturbance ……………. 8
2.1.7 The Sizing Confliction of 6T SRAM ………………………... 10
2.2 The Architecture of SRAM Array ………………………….……... 11
2.2.1 Non-Bit-Interleaving Architecture …………………………... 12
2.2.2 Bit-Interleaving Architecture ………………………………... 14
2.2.3 Large Signal Sensing Scheme …………………………..…... 15
2.2.4 Differential Sensing Scheme ………………………………... 17
2.3 Global Variation and Local Variation Issue ……………..………... 19
2.4 The Design Methodology of Assistant Circuits …………………... 20
2.4.1 Low-Power Technique ………..……………... 20
2.4.2 Write-Assistant Circuits ……………………………………... 23
2.5 Summary …………………………..………………... 28
Chapter 3 The Design of 256Kb Low-Power 6T SRAM …………….……... 29
3.1 Introduction ……………………………..……... 29
3.2 Low-Power Technique …………………………... 31
3.2.1 Power-Gating Technique ……………………..……... 31
3.2.2 Low-Swing Sensing Scheme ………………………………... 33
3.3 Write Assistant Circuits …………………………………………... 36
3.4 Summary …………………………..………………... 40
Chapter4 Simulation Results and Chip Implementation .…………………... 41
4.1 Simulation Results .……………………………………..………... 41
4.2 Test Chip Implementation .…………...………... 47
4.3 Measurement Flow .……………………………..……... 49
Chapter 5 Conclusion .………………………………………………...……... 51
Reference .………………………………...…………………..…... 52

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