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研究生:薛菘昀
研究生(外文):Hsueh, Sung-Yun
論文名稱:考慮溫度效應影響的統計型軟性電子錯誤率分析架構
論文名稱(外文):A Temperature-Aware Statistical Soft-Error-Rate Analysis Framework for Combinational Circuits
指導教授:溫宏斌
指導教授(外文):Wen, Hung-Pin
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:102
語文別:英文
論文頁數:42
中文關鍵詞:軟性電子錯誤率
外文關鍵詞:soft errors
相關次數:
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奈米級CMOS 電路設計的可靠度分析中,軟性電子錯誤率被視為重要的議題之一。在篇論文中,45nm 製程下的電路c17 (ISCAS’85)的軟性電子錯誤率隨著溫度的變化在本文中第一次被分析。實驗結果發現當溫度由25°C 上升至125°C,軟性電子錯誤率增加超過2 倍。因此,我們提出了一種考慮溫度效應影響下的統計型軟性電子錯誤率分析架構,能夠準確且快速地計算出電路的軟性電子錯誤率,並且同時考慮製程的變異以及溫度效應。藉由實驗結果發現,我們的架構與蒙地卡羅SPICE 模擬相比,達到加速的效果,並實現了高精確度的估計(<4%的誤差)。
Soft error has become one of the most critical reliability issues for nano-scaled CMOS designs. Many previous works discovered that the pulse width due to a particle strike on the device increases with temperature, but its chip-level effect has not yet been investigated with soft-error-rate (SER). Therefore, in this paper, a combinational circuit (c17 from ISCAS‘85) using a 45nm CMOS technology is first observed under different temperatures for SER. As a result, a SER increase (2X more) is found on c17 as the ambient temperature elevates from 25 °C to 125 °C. Second, along with growing design complexity, the operational temperatures of gates are distributed in a wide range and can be 2 to 3 times higher than the ambient temperature in reality. Therefore, we are motivated to build a temperature-aware SSER analysis framework (TASSER) that integrates statistical cell modeling to consider the ambient temperature (Ta) and the temperature variation (Tv), simultaneously. Experimental result shows that our SER analysis framework is highly efficient (with four-order speed-ups) and accurate (with only <4% errors), when compared with Monte-Carlo SPICE simulation.
List of Tables iv
List of Figures v
1 Introduction 1
2 Background 7
2.1 Statistical Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Statistical Soft Error Rate Analysis . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Temperature Effect on Device . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Soft Error Rate Under Temperature Effect 12
3.1 Temperature Impact to SET at Cell Level . . . . . . . . . . . . . . . . . . 13
3.2 Chip-level SER under Temperature Effect . . . . . . . . . . . . . . . . . . 14
4 Temperature-aware SSER Analysis (TASSER) 19
4.1 Overall flow of SER analysis . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Temperature-aware Cell Modeling . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Electrical-Pulse Propagation . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Chip-level SER Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1 Logic-Probability Computation . . . . . . . . . . . . . . . . . . . 27
4.4.2 Electrical-Probability Computation . . . . . . . . . . . . . . . . . 28
5 Experimental Results 31
6 Conclusion 38
Bibliography 40
[1] R. Rajaraman et al., “SEAT-LA:A soft error analysis tool for combinational logic,” in Proc. VLSI Design, pp. 499-502, 2006.
[2] K. Ramakrishnan et al., “Variation impact on SER of combinational circuits,” in Proc. Intl Symposium on Quality of Electronic Design (ISQED), pp.911-916, 2007.
[3] M. Natasa et al., “Process Variability-Aware transient fault modeling and analysis,” in Proc. Intl Conference on Computer-Aided Design (ICCAD), pp. 685-690, 2008.
[4] Austin C.-C. Chang et al. ”CASSER: A Closed-form Analysis Framework for Statistical Soft Error Rate,”in IEEE trans. Very Large Scale Integration (VLSI) Systems, vol. , pp. Oct. 2012.
[5] G.C. Messenger, “Collection of charge on junction nodes from Ion Tracks,” in IEEE Trans. Nuclear Science, vol. 29, pp. 2024-2031, 1982.
[6] P. Shivakumar et al., “Modeling the effect of technology trends on the soft error rate of combinational logic,” in Proc. Dependable Systems and Networks (DSN), pp. 389-398, 2002.
[7] Z. Ming et al., “A soft error rate analysis (SERA) methodology,” in Proc. Intl Conference on Computer-Aided Design (ICCAD), pp. 111-118, 2004.
[8] M. Bagatin et al. “Factors impacting the temperature dependence of soft errors in commercial SRAMs,” Radiation and Its Effects on Components and Systems (RADECS), European Conference, pp. 100-106, 2008.
[9] S. Chen et al. “Temperature dependence of digital SET pulse width in bulk and SOI technologies,” in IEEE Trans. Nuclear Science, vol. 55, no. 6, pp. 2914-2920, 2008.
[10] J. Matthew et al. “Temperature Dependence of Digital Single-Event Transients in Bulk and Fully-Depleted SOI Technologies,” in IEEE Trans. Nuclear Science, vol. 5. 6, no. 6, pp. 3115-3121, 2009.
[11] J. Matthew et al. “The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology,” Reliability Physics Symposium, IEEE International, pp. 170-173, 2009.
[12] J. Matthew et al. “Single-event transient measurements in nMOS and pMOS transistors in a 65-nm bulk CMOS technology at elevated temperatures,” in IEEE Trans. Device and Materials Reliability, vol. 11, no. 1, pp. 179-186,
2011.
[13] P.-Y. Huang et al. “Full-chip thermal analysis for the early design stage via generalized integral transforms,” in IEEE Trans. Very Large Scale Integration (VLSI) Systems,vol. 17, no. 5, pp. 613-626, 2009.
[14] Y. Yang et al., “ISAC: Integrated Space and Time Adaptive Chip-Package Thermal Analysis,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 86-99, 2007.
[15] NANGATE. [Online]. www.nangate.com
[16] P. Shivakumar et al., “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in Proc. Dependable Systems and Networks (DSN), pp. 389 - 398, 2002.
[17] B. Zhang et al., “FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs,” in Proc. Intl Symposium on Quality Electronic Design (ISQED), pp. 755-760, 2006.
[18] M. Zhang et al., “Soft-Error-Rate-Analysis (SERA) Methodology,” in IEEE Trans. on Computer Aided Design (TCAD), vol. 25, no.10, pp. 2140 - 2155, 2006.
[19] S. Krishnaswamy et al., “On the role of timingmasking in reliable logic circuit design,” in Proc. Design Automation Conf.(DAC), pp. 924-929, Jul. 2008.
[20] C. E. Clark, “The greatest of finite set of random variables,” in Operation Research, pp. 145-162, March-April 1961.
[21] M. Cain, “The moment-generating function of the minimum of bivariate normal random variables,” in The American Statistician, vol. 48, pp. 124- 125, May 1994.
[22] C. Visweswariah et al., “First-Order Incremental Block-Based Statistical Timing Analysis,” in Proc. Design Automation Conf. (DAC), pp. 331 - 336, 2004.
[23] H.K. Peng et al., “On Soft Error Rate Analysis of Scaled CMOS Designs - A Statistical Perspective,” in Proc. Intl Conf. on Computer-Aided Design (ICCAD), pp. 157 - 163, 2009
[24] L.J. Bainet al., “Introduction to Probability and Mathematical Statistics,” 2nd ed, 2000.
[25] N. Miskov-Zivanov et al., “MARS-C: modeling and reduction of soft errors in combinational circuits,” Proc. Design Automation Conf. (DAC), pp. 767-772,Jul. 2006
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