臺灣博碩士論文加值系統

本篇論文針對電動車內搭載的電池電源模組所使用之鋰電池進行監控研究。在電池陣列中每顆鋰電池上加入一個電池電壓監控IC (BMIC)，利用BMIC將鋰電池目前的電壓轉換成數位訊號，傳至後方的微處理器進行進一步的處理。考慮到車用的溫度及電池為IC唯一的電源來源，必須利用前端電路 (Frond End Circuit)來降低溫度對電路產生的影響及提供電源給各部分的子電路。同時BMIC對於鋰電池而言是額外的消耗，必須盡可能降低其所需使用的功耗，設計上不僅大幅度的降低後方電路供應電壓，此外我們還對SAR ADC的架構進行改良，使用電容式分壓電路來進行訊號取樣及採用單一參考電壓來進行切換，最後完成再10KHz取樣速度下僅消耗51.3μW的監測電路(不含前端電路) ，使用TSMC 0.25μm HV 1P5M CMOS製成來實現與驗證此系統。

This thesis focuses on the monitoring system of the high voltage lithium battery modules of electric vehicles. We will equip every single lithium battery with a battery management IC (BMIC). Using the BMIC to convert battery voltage into digital codes, and then transmit the digital codes to microprocessor for further analyzing. A Frond End circuit is implemented to suppress the temperature effect and offer the power supply to other circuits. In addition, BMIC is extra power consumption for lithium battery, so it has to decrease the power dissipation. It is not only reducing the supply voltage but also modifying the architecture of SAR ADC. Using the voltage divider implemented by capacitor to sample the signal and single reference voltage to complete the conversion. Finally, the proposed architecture has a power of 51.3μW(Frond End circuit is excluded) and at 10kHz sampling rate. The chip is realized in TSMC 1P5M 0.25μm HV mixed signal CMOS process.

摘 要 i
Abstract ii
誌謝 iii
Table of Contents iv
List of Tables vii
List of Figures viii
Chapter 1 1
Introduction 1
1.1 Motivation 4
1.2 Thesis Organization 5
Chapter2 6
Lithium battery voltage monitoring system 6
2.1 Introduction 6
2.2 The battery voltage monitoring system. 7
2.2 The specification of data converter 11
2.2.1 Static Parameter 12
2.2.2 Dynamic Parameter 14

Chapter3 18
Frond End Circuits 18
3.1 Introduction 18
3.2 Voltage Divider 19
3.3 Band-gap Reference Circuit 22
3.3.1 Positive Temperature Coefficient Voltage 22
3.3.2 Negative Temperature Coefficient Voltage 23
3.3.3 Current mode band-gap 24
3.4 Low Dropout Voltage Regulator 27
Chapter4 32
Analog to Digital Converter Circuit 32
4.1 Introduction 32
4.2 DAC 34
4.2.1 The determination of unit capacitor 34
4.2.2 Capacitor array architecture 35
4.3 Sample &; Hold 36
4.3.1 Design Consideration 36
4.3.2 Circuit architecture 40
4.4 Successive approximation register (SAR) 41
4.5 Comparator 44
Chapter5 48
Layout and Simulation Result 48
5.1 Chip Layout 48
5.2 Simulation Results 50
5.3 Performance Comparison 55
5.4 Measurement Consideration 56
Chapter 6 57
Conclusion 57
6.1 Conclusion 57
6.2 Future Work 58
References 59

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