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研究生:廖翊君
研究生(外文):Yi-chun Liao
論文名稱:適用於可見光通訊系統之實係數快速傅立葉轉換的單路徑延遲回授架構設計
論文名稱(外文):Design of Real FFT SDF Architecture for Visible Light Communication
指導教授:蔡佩芸
指導教授(外文):Pei-yun Tsai
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:87
中文關鍵詞:可見光通訊實係數快速傅立葉轉換單路徑延遲回授架構
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可見光通訊系統(Visible Light Communication,VLC)主要是透過LED照明設備發出肉眼無法察覺的高頻率明暗閃爍之可見光,在不影響日常照明的使用下同時傳遞資料訊息。本論文使用OFDM技術來減輕符際干擾(Inter Symbol Interference,ISI)等問題,在訊號編碼上使用QPSK。本篇所模擬VLC系統的取樣頻率為200MHz,其中OFDM使用64點的FFT,OFDM symbol的長度為360ns,我們模擬不同房間大小之系統效能,其中房間大小為(7.73 m, 6.6 m, 2.8 m)之系統效能在〖SNR〗_e = 15 dB時,系統之位元錯誤率(Bit Error Rate,BER)可達到10-5至10-6。由於基頻訊號是對光的強度作調變,在時域的訊號將只會是純實數,因此使用實係數之(Real FFT,RFFT)來降低運算量。
本論文提出RFFT的單路徑延遲回授(Single-path Delay Feedback,SDF)架構,利用Hermitian symmetry的共軛對稱特性將複數FFT的多餘頻域輸出訊號予以移除,以節省運算量和硬體複雜度。並根據實複數值混和路徑型態的訊號流程圖(Signal Flow Graph,SFG)來設計,主要原因除了增加硬體的使用率之外,也是為了降低複數型態延遲單元的數量。我們針對第三級的複數乘法運算做適當的重新排程,再搭配硬體共用的方式以更有效率地使用延遲單元。所提出的硬體使用了(4 log_2⁡N-6)個實數加法器、(log_8⁡N-3/2)個複數乘法器和(9N/8-1)個實數延遲單元,因此相較於其他RFFT的多路徑延遲交換(Multi-path Delay Commutator,MDC)架構以及CFFT的SDF架構,我們所使用的複數乘法器數目也相對的比較少。

Visible light communication (VLC) is an alternative of wireless communication and it transmits signals by LEDs illumination. In this paper, we modulate signals by OFDM technology to mitigate the inter symbol interference (ISI) caused by multipath effect and encode transmitted signals by QPSK. The sampling frequency is 200 MHz and the size of FFT and CP period is 64 point and 8 samples. Hence, the OFDM symbol period is 360 ns in the VLC system that we simulate. We simulate the VLC system in different room sizes. In the simulation of special room(7.73 m, 6.6 m, 2.8 m), a bit error rate (BER) of 10-5 to 10-6 is achieved under the 〖SNR〗_e = 15 dB. The OFDM baseband signal is used to modulate the LED intensity, and therefore the signals on the time domain will be only real value. Hence, we can use the real FFT (RFFT) to reduce operation.
This paper presents the single-path delay feedback (SDF) architecture for the FFT with real input samples. We take the advantage of Hermitian symmetry to save the computation and hardware complexity. The proposed N-point real FFT SDF architecture is based on the hybrid data-path SFG which is used to increase the hardware utilization and to reduce latency. With the proper scheduling in the stage 3 of the RFFT SDF architecture, we can use delay element efficiently by hardware sharing. Therefore, the proposed SDF architecture only requires (4 log_2⁡N-6) real adders, (log_8⁡N-3/2) complex multipliers and (9N/8-1) real delay elements. The hardware complexity is fewer than several real FFT multi-path delay commutator (MDC) architecture and complex FFT SDF architecture.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第1章 緒論 1
1.1 簡介與研究動機 1
1.2 論文架構 2
第2章 室內可見光通訊系統介紹 3
2.1 可見光通訊與射頻通訊 3
2.2 室內無線可見光通訊基本架構 6
2.2.1 傳送端 6
2.2.2 室內通道環境 8
2.2.3 接收端 9
2.3 訊號調變 10
2.3.1 開關控鍵調變 (OOK) 10
2.3.2 可調式脈衝準位調變 (VPPM) 12
2.3.3 Multiple PPM (MPPM) 13
2.3.4 用於VLC之正交多頻分工技術 (Optical OFDM) 14
第3章 室內無線可見光通訊系統模擬 17
3.1 室內通道環境建設 17
3.1.1 通道模型統計特性 19
3.1.1.1 LOS 路徑 20
3.1.1.2 Non-LOS路徑 23
3.1.2 延遲擴展 (Delay Spread) 27
3.1.3 通道脈衝響應h(t) 28
3.2 模擬之optical OFDM系統 29
3.2.1 模擬系統之參數設定 30
3.2.2 系統架構圖 31
3.2.2.1 Optical OFDM - 傳送端 31
3.2.2.2 Optical OFDM - 通道 32
3.2.2.3 Optical OFDM - 接收端 33
3.2.3 模擬系統之效能評估 33
第4章 用於運算實數序列的快速傅立葉轉換演算法 37
4.1 傳統快速傅立葉演算法與硬體架構 37
4.1.1 不同基數之DIF演算法介紹 38
4.1.1.1 Radix-2 38
4.1.1.2 Radix-22 (Radix-4) 39
4.1.1.3 Radix-23 (Radix-8) 41
4.1.2 Pipelined-based硬體架構 42
4.1.2.1 單路徑延遲回授架構 42
4.1.2.2 多路徑延遲交換架構 43
4.1.2.3 SDF與MDC架構比較 44
4.2 使用複數FFT運算實數序列 46
4.2.1 直接使用複數FFT 46
4.2.2 Packing Algorithm 47
4.2.3 Doubling Algorithm 48
4.2.4 使用CFFT運算實數序列之演算法比較 49
4.3 實係數之快速傅立葉演算法 50
4.3.1 複數值路徑 (Complex-valued Path) [24] 51
4.3.2 全實數值路徑 (All Real-valued path) [26] 52
4.3.3 實複數值混和路徑 (Hybrid-valued path) [25] 52
4.4 所提出之新的運算排程方法 53
4.4.1 各運算層級之運算單元處理 55
4.4.2 各運算層級之延遲單元處理 59
第5章 硬體架構設計與實現 62
5.1 硬體設計流程 62
5.2 硬體介紹 64
5.2.1 SDF RFFT之硬體區塊 64
5.2.2 Post-processing &; Reorder之硬體區塊 70
5.3 字元長度 76
5.4 硬體實現之結果與比較 79
第6章 結論 83
參考文獻 84

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[25] Ayinala M. and Parhi K.K., “FFT architectures for real-valued signals based on radix-23 and radix-24 algorithms,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 9, pp. 2422-2430, Feb. 2013
[26] Salehi S.A., Amirfattahi R. and Parhi K.K., “Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT with Real Datapaths,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, No. 8, pp. 507-511, Aug. 2013
[27] Ayinala M., Brown M. and Parhi K.K., “Pipelined Parallel FFT Architectures via Folding Transformation,” IEEE Transactions on VLSI Systems, Vol. 20, No. 6, pp. 1068-1081, June 2012.
[28] T. D. Chiueh and Pei-Yun Tsai, “OFDM Baseband Receiver Design for Wireless Communications,” John Wiley, 2007.(ISBN: 978-0-470-82234-0)
[29] Elgala H., Mesleh, R. and Haas, H., “Practical Considerations for Indoor Wireless Optical System Implementation using OFDM,” IEEE Telecommunications, pp. 25-29, June 2009

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