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研究生:丁韋文
研究生(外文):Wei-Wen Ding
論文名稱:環繞式閘極電晶體元件模型開發
論文名稱(外文):Compact Modeling of Gate-All-Around MOSFETs
指導教授:江孟學鄭岫盈
指導教授(外文):Meng-Hsueh ChiangShiou-Ying Cheng
口試委員:許育銘朱閔聖葉昇平江孟學鄭岫盈
口試委員(外文):Yu-Ming HsuMing-Shang ChuSan-Pin YehMeng-Hsueh ChiangShiou-Ying Cheng
口試日期:2014-07-19
學位類別:碩士
校院名稱:國立宜蘭大學
系所名稱:電子工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:65
中文關鍵詞:環繞式閘極電晶體
外文關鍵詞:Gate-All-Around MOSFET
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根據莫爾定律,元件製程技術不斷地進步使得電晶體尺寸持續微縮,因而推動VLSI技術的成長,而尺寸微縮具有較高封裝密度、較高電路速度以及較低的功率消耗等優點,但也產生了許多物理上的限制與問題的發生,如:短通道效應、DIBL等,都是未來在電晶體微縮過程中必須被解決的問題。
為解決上述的問題,必須提升短通道電晶體的閘極控制能力,其中多重閘極電晶體架構,被視為改善短通道效應及提升閘極控制能力的有效方法之一,其中包含:雙閘極電晶體、鰭式電晶體、三閘極電晶體、與環繞式閘極電晶體等,其中,以環繞式閘極電晶體被視為具有持續微縮能力的重要架構。本論文採用Verilog-A語言並配合SPICE電路模擬軟體來建置環繞式閘極電晶體,並開放設計參數方便使用者使用。
環繞式閘極電晶體是三維的立體結構,所以,在推導電晶體中心與表面電位時,為加快模擬軟體的計算時間與收斂性問題,把三維方向性的單一電位方程式縮減為通道方向(一維方向,中心電位)與中心到表面方向(二維方向,表面電位)的兩個方程式,之後把計算的電位帶入至次臨界區電流方程式,強反轉區電流則是使用環繞式閘極電晶體電流方程式求值,最後將使用次臨界區與強反轉區電流方程式作為兩個邊界帶入平滑曲線方程式中求出電流。最後將設計完成的元件模型應用於電路上進行模擬,以確保電路使用上的可靠性,並計算所需消耗之功率,以確保在節能意識中能夠保持應有的效能與優秀的功耗表現。
Following Moore's Law, CMOS transistors continue to scale. Many small-geometry effects have surfaced such as short-channel effects, limiting the device performance. In order to overcome the scaling issues, improving device gate capability is needed. Multi-gate transistor architecture is regarded as one of the most effective ways to improve the short channel effects and enhance the gate controllability. Multi-gate transistors include: Double gate MOSFET, FinFET, Tri-gate MOSFET and Gate-All-Around MOSFET. Among them, Gate-All-Around transistor is regarded as an important framework for continuing scaling capabilities. In this work, we use Verilog-A to develop the SPICE device models and to provide parameters for VLSI designers.
Gate-All-Around MOSFETs are three dimensional structures. In calculating the center and surface potentials of the transistor, in order to speed up the simulation time and avoid convergence problems, three-dimensional equations are reduced to one-dimensional and two-dimensional equations. Then, we use calculated potential to evaluate current. Finally, we use the complete model for circuit simulation to ensure a reliable model.
摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 IX
Chapter 1. 前言 1
1.1 金氧半場效電晶體元件介紹與發展背景 2
1.2 研究動機 3
1.3 軟體簡介 3
1.4 章節架構 4
Chapter 2. 多重閘極電晶體元件的發展與趨勢 5
2.1 多重閘極電晶體元件介紹 5
2.1.1 多重閘極電晶體元件電氣特性比較 8
2.2 各種多重閘極電晶體元件精簡模型介紹 11
Chapter 3. 以Verilog-A開發環繞式閘極電晶體元件模型 15
3.1 環繞式閘極電晶體元件於SOI晶圓之結構與特性 15
3.2 元件模型架構 16
3.2.1 加入短通道微縮效應的次臨界區電位模組 16
3.2.2 通道電流模組概述 20
3.2.3 次臨界區電流計算模組 20
3.2.4 反轉區電流計算模組 23
3.2.5 次臨界區與反轉區調合模組 26
Chapter 4. 加入物理修正模組與電荷模組之環繞式閘極電晶體元件模型 27
4.1 有效遷移率 28
4.2 結構角落效應修正 31
4.3 源極與汲極的串聯電阻效應 33
4.4 多重閘極電晶體元件模型之電荷推導 35
4.4.1 不同多重閘極電晶體元件之電荷比較 35
4.4.2 環繞式閘極電晶體電荷電流推導與模擬結果 38
4.5 元件電氣特性模擬結果分析 41
Chapter 5. 電路應用與近似臨界電壓理論介紹 48
5.1 應用電路架構介紹與模擬分析 48
5.1.1 反相器 48
5.1.2 隨機靜態存取記憶體 51
5.2 近似臨界電壓理論介紹 55
Chapter 6. 結論 58
附錄 A 符號表 59
附錄 B 元件模型參數表 61
參考文獻 62

[1]Bo Yu, Jooyoung Song, Yu Yuan, Wei-Yuan Lu, and Yuan Taur, “A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs,” IEEE Transactions on electron devices, Vol. 55, No. 8, pp. 2157-2163, 2008.
[2]Jooyoung Song, BoYu, Yu Yuan, and Yuan Taur, “A Review on Compact Modeling of Multiple-Gate MOSFETs,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 8, pp. 1858-1869, 2009.
[3]Juan Pablo Duarte, Sung-Jin Choi, Dong-Il Moon, Jae-Hyuk Ahn, Jee-Yeon Kim, Sungho Kim, and Yang-Kyu Choi, “A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part I: Charge Model,” IEEE Transactions on Electron Devices, Vol.60, No. 2, pp. 840-847, 2013.
[4]Open Verilog International, “Verilog-A Language Reference Manual Version 1.0, August 1, 1996,” available online : http://www.verilog.org/verilog-ams/htmlpages/public-docs/lrm/VerilogA/verilog-a-lrm-1-0.pdf.
[5]Eric Vogel, “Technology and metrology of new electronic materials and devices,” Nature Nanotechnology 2, pp. 25-32, 2007.
[6]Isabelle Ferain, Cynthia A. Colinge and Jean-Pierre Colinge, “Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors,” Nature 479, pp. 310-316, 2011.
[7]D. Munteanu, J. L. Autran, V. Ferlet-Cavrois, P. Paillet, J. Baggio and K. Castellani, ” 3D Quantum Numerical Simulation of Single-Event Transients in Multiple-Gate Nanowire MOSFETs,” IEEE Transactions on Nuclear Science, Vol. 54, No. 4, pp. 994-1001, 2007.
[8]Jong-Tae Park and Jean-Pierre Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” IEEE Transactions on Electron Devices, Vol. 49, pp. 2222-2229, 2002.
[9]Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, T.-J. King Liu, and W.-C. Hsu, “6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs,” Proc. 2013 Internat. Symp. VLSI- Technology, Systems and Applications, pp. 1-2, 2013.
[10]Christopher P. Auth and James D. Plummer, “Scaling Theory for Cylindrical, Fully-Depleted, Surrounding-Gate MOSFET’s,” IEEE Electron Device Letters, Vol. 18, No. 2, pp. 74-76, 1997.
[11]Ran-Hong Yan, Abbas Ourmazd and Kwing F. Lee, “Scaling the Si MOSFET: From Bulk to SO1 to Bulk,” IEEE Transactions on Electron Devices, Vol. 39. No. 7, pp. 1704-1710, 1992.
[12]Jean-Pierre Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics, Vol. 48, No. 6, pp. 897-905, 2004.
[13]Hamdy Abd El Hamid, Benjamin Iñíguez and Jaume Roig Guitart, “Analytical Model of the Threshold Voltage and Subthreshold Swing of Undoped Cylindrical Gate-All-Around-Based MOSFETs,” IEEE Transactions on Electron Devices, Vol. 54, No. 3, pp. 572-579, 2007.
[14]Romain Ritzenthaler, François Lime, Olivier Faynot, Sorin Cristoloveanu and Benjamin Iñiguez, “3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors,” Solid-State Electronics, pp. 94-102, 2011.
[15]Gen Pei, Jakub Kedzierski, Phil Oldiges, Meikei Ieong and Edwin Chih-Chuan Kan, “FinFET Design Considerations Based on 3-D Simulation and Analytical Modeling,” IEEE Transactions on Electron Devices, Vol. 49, No. 8, pp. 1411-1419, 2002.
[16]D. Jiménez, B. Iñíguez, J. Suñé, L. F. Marsal, J. Pallarès, J. Roig, and D. Flores, “Continuous Analytic I–V Model for Surrounding-Gate MOSFETs,” IEEE Electron Device Letters, Vol. 25, No. 8, pp. 571-573, 2004.
[17]Jim Armstrong, “Natural Cubic Splines,” TechNote TN-05-001, 2005. Available online: http://algorithmist.net/docs/spline.pdf
[18]Narain Arora, MOSFET MODELING FOR VLSI SIMULATION: Theory and Practice, 2007.
[19]François Lime, Benjamin Iñiguez and Oana Moldovan, “A Quasi-Two-Dimensional Compact Drain–Current Model for Undoped Symmetric Double-Gate MOSFETs Including Short-Channel Effects,” IEEE Transactions on Electron Devices, Vol. 55, No. 6, pp. 1441-1448, 2008.
[20]Jin-Woo Han, Choong-Ho Lee, Donggun Park and Yang-Kyu Choi, “Quasi-3-D Velocity Saturation Model for Multiple-Gate MOSFETs,” IEEE Transactions on Electron Devices, Vol. 54, No. 5, pp. 1165-1170, 2007.
[21]Yuan Taur and Tak H. Ning, Fundamentals of modern VLSI Devices, International Student Edition, 2010.
[22]Benjamin Iñíguez, David Jiménez, Jaume Roig, Hamdy A. Hamid, Lluís F. Marsal and Josep Pallarès, “Explicit Continuous Model for Long-Channel Undoped Surrounding Gate MOSFETs,” IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp. 1868-1873, 2005.
[23]The International Technology Roadmap for Semiconductors, 2012 update. Available online: http://www.itrs.net/
[24]Zhi-Yuan Cui, Jung-Woong Park, Chan-Soo Lee, and Nam-Soo Kim, “Integration of CMOS Logic Circuits with Lateral Power MOSFET,” IEEE Intelligent Systems Modelling & Simulation, pp. 615-618, 2013.
[25]B. Calhoun and A. Chandrakasan, “A 256 kb sub-threshold SRAM in 65 nm CMOS,” IEEE International SOLID-State Circuits Conference, pp.628-629, 2008.
[26]Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi and Roghayeh Saeidi, “A 32kb 90nm 9T -cell Sub-threshold SRAM with Improved Read and Write SNM,” IEEE Design & Technology of Integrated Systems in Nanoscale Era, pp. 104-107, 2013.
[27]Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao, “Improved Write Margin 6T-SRAM for Low Supply Voltage Applications,” IEEE International SOC Conference, pp.223-226, 2009.
[28]Intel 2011 Developer Forum IDF 2011, Vice President & CTO Justin Rattner’s Presentation.
[29]B.H. Calhoun and D. Brooks, “Can Subthreshold and Near-Threshold Circuits Go Mainstream?,” IEEE Micro, Vol.30, No. 4, pp. 80-85, 2010.
[30]R. G. Dreslinski, M. Wieckowski, D. Blaauw, Sylvester, D. Sylvester, “Near-Threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits,” Proceedings of the IEEE, vol. 98, No. 2, pp. 253-266, 2010.
[31]H. Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy and S. Borkar, “Near-threshold voltage (NTV) design — Opportunities and challenges,” ACM/EDAC/IEEE
Design Automation Conference (DAC), pp. 1149-1154, 2012.
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