臺灣博碩士論文加值系統

銲線在半導體封裝製程中占有舉足輕重的地位，隨著3C產品蓬勃發展半導體市場需求也加速成長，降低製造成本以獲取更大的利潤，一直是企業努力的方向之一，其中增加製程良率、減少製程錯誤更是降低製造成本的關鍵因素之一。
如何防止銲線製程錯誤，以提高產品良率減少製造的損失進而降低生產成本的關鍵在製程程式，其中製程參數與銲線圖是造成製程錯誤的主因。本論文主要重點在於如何解析製程程式，並撰寫程式取得製程參數與銲線圖資訊以利後續核圖驗證、自動下載製程程式給機台作業避免人為手動選擇而造成的錯誤、取得正在執行中的製程程式、設計製程參數與銲線圖核圖驗證方法與機制。
本論文針對製程參數與銲線圖分別提出對應的管控方法，製程參數管控，依參數群組管控每個關鍵參數在該群組的範圍值，使每條打線套用的參數值都在允許的範圍內；銲線圖管控，依打點間相對位置的X、Y偏移量，來管控執行中的製程程式與標準製程程式其誤差在允差範圍內。經實驗證明確實能有效避免銲線製程錯誤，且核圖驗證最長所需時間為6.087秒，對生產的衝擊很小可忽略不計。

Wire bonding process plays a decisive role in semiconductor device fabrication during assembly and packaging process. The vigorous growth in 3C products has led to considerable increases in the market needs of semiconductor. The enterprise is always trying every attempt on profits increase, the way to reduce manufacturing costs is one of them. As a matter of fact, increase manufacturing yield and lower processing errors are the key factors of cutting down the manufacturing costs.
Recipe is the key point of preventing wrong bonding process while the incorrect recipe parameters values and bonding locations are the root causes. This thesis is mainly focused on the following topics:
1. Download recipes to equipment automatically to avoid operators choosing the wrong one.
2. Get the running recipe from equipment to ensure equipment is processing correctly.
3. Recipe data structure analysis that demonstrates how to retrieve the information of parameters values and bonding locations for the further use of bonding diagram verification.
4. Recipe modification monitor that activates the process program verification scenario.
5. Recipe parameters values and bonding diagram verification.
This thesis proposes the methodologies and mechanisms against the verification of parameters values and bonding diagrams. Recipe parameters are monitored against the corresponding groups and the values should be in the predefined range, whereas the bonding diagram is monitored by the bonding locations, the offset of X and Y coordinates compared with the golden Recipe should below the tolerated limitations. It has been proven to be feasible and effective by practical experiments. And the longest time it takes to verify is 6.087 seconds, hence the impact on production throughput is very trivial and could be ignored.

摘要 ...i
ABSTRACT ...ii
誌謝 ...iii
目錄 ...iv
圖目錄 ...vi
表目錄 ...ix
1 第一章、緒論 ...1
1.1 研究背景與動機 ...1
1.2 研究目的 ...4
1.3 研究方法 ...5
1.3.1 自動下載Golden Recipe ...7
1.3.2 當製程程式發生異動時自動執行核圖驗證 ...8
2 第二章、文獻探討 ...10
2.1 半導體封裝製程簡介 ...10
2.1.1 晶圓背磨（wafer back grinding） ...10
2.1.2 晶圓貼片（wafer mount） ...11
2.1.3 晶圓切割（wafer saw/die saw） ...12
2.1.4 黏晶（die bond） ...12
2.1.5 銲線（wire bond） ...13
2.1.6 封膠（molding） ...16
2.1.7 印字（mark） ...17
2.1.8 剪切/成型（trim/form） ...17
2.1.9 檢驗（inspection) ...18
2.1.10 IC測試（final test） ...18
2.2 半導體設備通訊規範 ...19
2.2.1 SECS主要訊息 ...19
2.2.2 SECS常用子訊息 ...20
2.2.3 Stream and Function ...20
2.2.4 設備控制通訊協定GEM ...25
2.2.5 SECS 通訊協定與資料結構 ...30
2.2.6 SECS-I ...31
2.2.7 SECS-II ...38
2.2.8 HSMS ...50
3 第三章、研究方法 ...56
3.1 自動下載標準製程程式 ...56
3.2 取得正在執行中的製程程式 ...60
3.3 解析製程程式 ...61
3.3.1 主程式檔 ...63
3.3.2 參考系統檔 ...63
3.3.3 銲線參數檔 ...64
3.3.4 銲線圖檔 ...65
3.4 製程程式異動偵測 ...67
3.5 銲線程式自動核圖驗證方法與機制 ...70
3.5.1 關鍵參數範圍值管控 ...70
3.5.2 打點位置允差管控 ...72
3.5.3 核圖驗證機制 ...76
4 第四章、實驗與分析 ...81
4.1 開發環境與工具 ...81
4.2 製程程式下載實驗 ...83
4.3 製程程式上傳實驗 ...89
4.4 銲線程式自動核圖驗證實驗 ...95
5 第五章、結論與未來研究 ...103
5.1 結論 ...103
5.2 未來研究與建議 ...104
參考文獻 ...105

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