跳到主要內容

臺灣博碩士論文加值系統

(34.204.169.230) 您好!臺灣時間:2024/03/03 01:14
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:陳亭諳
研究生(外文):Ting-An Chen
論文名稱:使用草稿記憶體之ARM程式於精準記憶體模型上的靜態最差執行時間分析工具
論文名稱(外文):A Tool for Static WCET Analysis with Accurate Memory Modeling for ARM Programs that Use Scratchpad Memory
指導教授:Steve W.Haga
指導教授(外文):Steve W.Haga
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:78
中文關鍵詞:記憶體模型草稿記憶體SWEETARM最差執行時間
外文關鍵詞:WCETmemory moduleSPMSWEETARM
相關次數:
  • 被引用被引用:0
  • 點閱點閱:148
  • 評分評分:
  • 下載下載:4
  • 收藏至我的研究室書目清單書目收藏:0
在即時系統中,為了保證系統的可靠性,每一個程序都必須在時間期限內完成,故在規劃程序的執行順序時提供精確的最差執行時間將會是重要的關鍵。
最差執行時間可以透過測量分析或者靜態分析來獲得,其中測量分析的方式並不能保證最差執行時間的可靠度,故在本論文中我們採用靜態分析的方式以確保最差執行時間的可靠度。
我們使用 SWEET (SWEdish execution time tool) 來提供ARM系統的最差執行時間,但SWEET的記憶體模型過於老舊以至於不能提供精確的最差執行時間。故本論文提供一個簡化的系統架構,對記憶體的寫入以及讀取動作所需要的執行時間做分析。本系統架構除了能夠對DRAM做執行時間的分析,也可以對草稿記憶體做執行時間的分析。除此之外,為了避免記憶體分配器過度最佳化最差執行路徑,本論文亦提供一個較有效率的方式產生近似最差執行路徑。
實驗結果顯示使用我們的記憶體模型來分析記憶體比起假設所有記憶體存取都為最差情況約可以改善43%~46%的最差執行時間。
In order to guarantee the reliability of the real-time system, each process should be complete before the deadline. Therefore, providing accurate WCET for scheduler would be a key factor.
WCET can derive by two method: measurement-base or static analysis. Since measurement-base cannot guarantee the safety of WCET, we use static analysis in this thesis.
In this thesis, we use SWEET (SWEdish execution time tool) to estimates WCET for ARM. Since the memory module of SWEET for ARM is out of date and cannot provide accurate WCET. Therefore, we propose a simplified architecture for analyzing the time costs of memory read accesses and memory write accesses. This method can not only derive the memory access time of DRAM but also SPM. Additionally, in order to prevent over-optimizing issue of allocator on WCET, we also provide a more efficient way to generate nearly worst case flow paths.
Experiment result shows our memory module can improve 43%~46% of WCET compares to the situation which assumed every memory access is worst.
1 INTRODUCTION.......................................................................................1
1.1. REAL-TIME SYSTEMS.............................................................................2
1.2. WORST CASE EXECUTION TIME ANALYZER.........................................3
1.2.1. Measurement-based Analysis ........................................................3
1.2.2. Static WCET Analysis......................................................................5
1.3. ARM SUPPORTED STATIC ANALYZER...................................................6
1.3.1. SWEET Develop by Mälardalen University.......................................6
1.3.2. SWEET Static Analyzer Supported ARM GCC.................................8
1.4. MEMORY MODULE FOR SWEET STATIC-ANALYZER............................9
2. RELATED WORK...................................................................................15
2.1. SWEET ANALYZER................................................................................15
2.1.1. SWEET Flow Analysis Phase.........................................................16
2.1.2. SWEET Low-Level Analysis Phase................................................18
2.1.3. SWEET Calculation Phase.............................................................20
2.2. ARM SUPPORTED SWEET....................................................................24
2.3. MEMORY MODELING............................................................................25
3. METHODOLOGY....................................................................................30
3.1. A DISCUSSION OF THE FACTORS THAT AFFECT THE DRAM ACCESS PATTERN ......................................................................................................30
3.2. THE SPECIFIC IMPACT OF THE IPB UPON THE MEMORY ACCESS ORDER..........................................................................................................32
3.3. DERIVING THE MEMORY AWARE WCET...............................................37
3.3.1. Deriving the Worst-case Time for Reads, WTOR...........................38
3.3.2. Deriving the Worst-case eXtra Time for Writes, WXTW..................44
3.3.3. A Discussion of Optimizations for Improving the WCET Quality and the Analysis Time for Our Algorithm ..............................................................54
3.4. PRODUCE THE NECFP..........................................................................58
4. EXPERIMENTS RESULTS......................................................................60
5. CONCLUSIONS......................................................................................64
6. REFERENCE.........................................................................................65
[1]SWEET (SWEdish Execution Time tool) Website.
[2]H. C. Fadia Nemer, Pascal Sainrat, Jean-paul Bahsoun, Marianne De Michiel "Papabench: a free real-time benchmark," 2006.
[3]W.-C. Hao, "Integrating the SWEET WCET Analyzer into ARM-GCC with Extra WCFP Information to Enable WCET-Targeted Compiler Optimizations," Master, Computer Science and Engineering, NSYSU, 2011.
[4]A. E. Jakob Engblom , Mikael Nolin, Jan Gustafsson, Hans Hansson, "Worst-Case Execution-Time Analysis for Embedded Real-Time Systems " International Journal on Software Tools for Technology Transfer, 2003.
[5]P. P. Raimund Kirner, "Classification of WCET Analysis Techniques," presented at the Proceeding ISORC ''05 Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing 2005.
[6]G. Bernat, Colin, A., Petters, S.M., "WCET analysis of probabilistic hard real-time systems " presented at the Real-Time Systems Symposium, 2002.
[7]J. E. Reinhard Wilhelm, Andreas Ermedahl,Niklas Holsti, Stephan Thesing, David Whalley, Guillem Bernat, Christian Ferdinand, Reinhold Heckmann, Tulika Mitra, Frank Mueller, Isabelle Puaut, Peter Puschner, Jan Staschulat, Per Stenström,, "The worst-case execution-time problem—overview of methods and survey of tools," ACM Transactions on Embedded Computing Systems (TECS), 2008
[8]I. Wenzel, Kirner, R., Rieder, B., Puschner, P., "Measurement-based worst-case execution time analysis " presented at the Software Technologies for Future Embedded and Ubiquitous Systems, 2005.
[9]C.-Y. Yen, "Worst Case Execution time Analysis Support for the ARM Processor Using GCC," Master, Computer Science and Engineering, NSYSU, 2009.
[10]D. T. Wang, Modern DRAM Memory Systems: Performance Analysis and Scheduling Algorithm, 2005.
[11]R. Banakar, Steinke, S., Bo-Sik Lee ; Balakrishnan, M., Marwedel, P., "Scratchpad memory: a design alternative for cache on-chip memory in embedded systems," presented at the Hardware/Software Codesign, 2002.
[12]C.-Y. Wu, "A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time," Master, Computer Science and Engineering, NSYSU, 2009.
[13]J.-y. Bai, "A Memory-Realistic SPM Allocator with WCET/ACET Tunable Performance," Master, Computer Science and Engineering, NSYSU, 2009.
[14]H.-J. Fang, "Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance," Master, Computer Science and Engineering, NSYSU, 2011.
[15]A. Ermedahl, A Modular Tool Architecture for Worst-Case Execution Time Analysis: VDM Verlag Saarbrücken, Germany, Germany ©2008 2008.
[16]SWEET (SWEdish Execution Time tool) manual
[17]R. C. Patrick Cousot, "Abstract interpretation: a unified lattice model for static analysis of programs by construction or approximation of fixpoints," presented at the Conference Record of the 4th Annual ACM SIPLAN-SIGACT Symposium on Principles of Programming Languages, 1977.
[18]C. Healy, Sjodin, M., Rustagi, V., Whalley, D., "Bounding loop iterations for timing analysis " presented at the Real-Time Technology and Applications Symposium, 1998.
[19]G. H. H. T. E. Cheatham, J. A. Townley, "Symbolic Evaluation and the Analysis of Programs " Software Engineering, IEEE Transactions, 1979.
[20]F. S. Andreas Ermedahl , Jakob Engblom, "Clustered Calculation of Worst-Case Execution Times," presented at the International conference on Compilers, architecture and synthesis for embedded systems 2003.
[21]F. Mueller, Whalley, D.B., "Fast instruction cache analysis via static cache simulation," presented at the Simulation Symposium, 1995., Proceedings of the 28th Annual, 1995
[22]C. A. Healy, Whalley, D.B., Harmon, M.G., "Integrating the timing analysis of pipelining and instruction caching," presented at the Real-Time Systems Symposium, 1995. Proceedings., 16th IEEE 1995
[23]F. Mueller, "Generalizing timing predictions to set-associative caches," presented at the Real-Time Systems, 1997. Proceedings., Ninth Euromicro Workshop on 1997
[24]Y.-T. S. Li, Malik, S., Wolfe, A., "Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches," presented at the Real-Time Systems Symposium, 1996., 17th IEEE 1996
[25]T. L. Thomas Lundqvist , Thomas Lundqvist, A WCET Analysis Method for Pipelined Microprocessors with Cache Memories, 2002.
[26]H. Ramaprasad, Mueller, F., "Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns," presented at the Real Time and Embedded Technology and Applications Symposium, 2005. RTAS 2005. 11th IEEE 2005.
[27]C. F. Christoph Cullmann, Gernot Gebhard, Daniel Grund, Claire Maiza, Jan Reineke, Benoît Triquet, Reinhard Wilhelm "Predictability Considerations in the Design of Multi-Core Embedded Systems " Ingénieurs de l''Automobile, 2010.
[28]A. Prakash, Patel, H.D., "An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture," presented at the Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2012 2012.
[29]C. B. Roman Bourgade, Hugues Cassé, Christine Rochange, Pascal Sainrat, "Accurate Analysis of Memory latencies for WCET Estimation," presented at the 16th International Conference on Real-Time and Network Systems, 2008.
[30]S. W. N. B. Jacob, D. T. Wang, Memory Systems: Cache, DRAM, Disk, 2008.
[31]L. W. Yiqiang Ding, Wei Zhang, "Bounding the Worst-Case DRAM Performance on Multicore Processors," Journal of Computing Science and Engineering, 2013.
[32]E. Q. Marco Paolieri, Francisco J. Cazorla, "Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions," ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia''12, LCTES''11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems, 2013.
[33]D. Jun Shao, B.T., "A Burst Scheduling Access Reordering Mechanism," presented at the High Performance Computer Architecture, 2007. HPCA 2007. IEEE 13th International Symposium on 2007.
[34]J. Hasan, Chandra, S., Vijaykumar, T.N., "Efficient Use of Memory Bandwidth to Improve Network Processor Throughput," presented at the Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on 2003.
[35]B. Akesson, Goossens, K., Ringhofer, M., "Predator: a Predictable SDRAM Memory Controller," presented at the Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2007 5th IEEE/ACM/IFIP International Conference on 2007.
[36]I. L. Jan Reineke, Hiren D. Patel, Sungjun Kim, Edward A. Lee, "PRET DRAM controller: bank privatization for predictability and temporal isolation," presented at the CODES+ISSS ''11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2011.
[37]H. Shah, Raabe, A., Knoll, A., "Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs," presented at the Design, Automation &; Test in Europe Conference &; Exhibition (DATE), 2012 2012.
[38]W. Z. Lan Wu, "Time Predictability DRAM Access Scheduling Algorithms for Real-Time Multicore Processors," presented at the Southeastcon, 2013 Proceedings of IEEE 2013.
[39]K. Zheng Pei Wu, Y., Pellizzoni, R., "Worst Case Analysis of DRAM Latency in Multi-Requestor Systems," presented at the Real-Time Systems Symposium (RTSS), 2013 IEEE 34th, 2013.
[40]I. S. Liu., Precision Timed Machines, 2012.
[41]WCET BENCHMARK.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊