隨著積體電路技術的快速發展，多處理器晶片（chip multiprocessors, CMPs）被廣泛使用於平行應用程序及即時應用程序。對於多處理器晶片而言，隨著晶片上處理器數量的持續增加，為了達到高性能及高處理能力（throughput），有效率的溝通是不可或缺的。因此，連接架構的設計對於整體系統的性能、面積及功率消耗發揮了重要的作用。由於晶片網絡（network-on-chip, NoC）和傳統的晶片上匯流排（on-chip bus）架構有其各自的優缺點，我們必需考慮系統的性能要求及應用程序的特性，以設計出適當的網絡連接架構。本論文針對多處理器晶片及多執行緒應用程序（multi-threaded application）提出並評估三種叢集式的連接架構：（1）叢集晶片網路架構，（2）階層匯流排架構，和（3）混合架構。實驗結果顯示對於多處理器晶片及多執行緒應用程序而言，同時考慮到性能及系統的擴充性，在三種叢集式的連接架構之中，叢集晶片網路架構是最實際的選擇。

With the rapid development of silicon technology, chip multiprocessor (CMP) are widely used for parallel applications and real-time applications. For CMPs, as the number of processors on a chip continues to increase, efficient communication is essential for achieving high performance and throughput. Therefore, the design of the interconnection architecture plays an important role in determining the performance, area, and power consumption of the overall system. Because network-on-chip (NoC) and traditional on-chip bus interconnection have their own advantages and disadvantages, we need to consider the system performance requirement and the application properties to design an appropriate network interconnection architecture. In this thesis, for CMPs and multi-threaded applications, we propose and evaluate three cluster-based interconnection architectures: (1) cluster-based NoC architecture, (2) hierarchical bus architecture, and (3) hybrid architecture. The experiment results show that considering both performance and scalability for CMPs and multi-threaded applications, cluster-based NoC architecture is the most practical choice among the three cluster-based interconnection architectures.

1 Introduction 1
2 Background and Motivation 4
2.1 Background 4
2.2 Motivation 6
3 Architecture 9
3.1 Cluster-based NoC Architecture 9
3.2 Hierarchical Bus Architecture 10
3.3 Hybrid Architecture 11
4 Evaluation Method 13
4.1 Full System Simulator 13
4.2 Bus Implementation 14
4.2.1 Behavior of Bus 15
4.2.2 Bus Input Arbiter 16
4.3 Network Interface 17
4.3.1 Cluster-based NoC Architecture Network Interface 18
4.3.2 Hierarchical Bus Architecture Network Interface 19
4.3.3 Hybrid Architecture Network Interface 20
5 Experimental Result 23
5.1 Experimental Setup 23
5.2 Effect of Cluster-based NoC Architecture 25
5.3 Results of Different Cluster-based Interconnection Architecture 26
5.4 Effect of Heavy Inter-cluster Traffic 28
6 Conclusions 33

[1] K. Olukotun, B. A. Nayfeh, L. Hammond, K. Wilson, and K. Chang, "The Case for a Single-Chip Multiprocessor," ACM Sigplan Notices, vol. 31, no. 9, pp. 2-11, 1996.
[2] W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proceedings of Design Automation Conference(DAC), pp. 684-689, 2001.
[3] M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli, "Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design," Proceedings of Design Automation Conference(DAC), pp. 667-672, 2001.
[4] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, "A Network on Chip Architecture and Design Methodology," Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 105-112, 2002.
[5] J. Kim, D. Park, C. Nicopoulos, N. Vijaykrishnan and C. R. Das, "Design and Analysis of an NoC Architecture from Performance, Reliability and Energy Perspective," Proceedings of the 2005 ACM Symposium on Architecture for
Networking and Communications Systems, pp. 173-182, 2005.
[6] M. M. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood, "Multifacet's General Execution-Driven Multiprocessor Simulator (GEMS) Toolset," ACM SIGARCH Computer Architecture News, vol. 33, no. 4, pp. 92-99, 2005.
[7] W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann Publishers, 2004.
[8] W. J. Dally, "Virtual-Channel Flow Control," IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, 1992.
[9] Interconnection Network. Retrieved August 1, 2013, from http://www.m5sim.org/Interconnection_Network
[10] E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Cost Considerations in Network on Chip," INTEGRATION, the VLSI Journal, Vol. 38, no. 1, pp. 19-42, 2004.
[11] Arteris, A Comparison of Network-on-Chip and Busses. Retrieved August 1, 2013, from http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html
[12] C. Benia, S. Kumar, J. P. Singh, and K. Li, "The PARSEC Benchmark Suite: Characterization and Architectural Implications," Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, pp. 72-81, 2008.
[13] S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," ACM SIGARCH Computer Architecture News, vol. 23, no. 2, pp. 24-36, 1995.
[14] N. Agarwal, T. Krishna, L.-S. Peh and N. K. Jha, "GARNET: A Detailed On-Chip Network Model inside a Full-System Simulator," IEEE International Symposium on Performance Analysis of Systems and Software(ISPASS), pp.
33-42, 2009.
[15] A. Bartolini, M. Cacciari, A. Tilli, L. Benini, M. Gries, "A Virtual Platform Environment for Exploring Power, Thermal and Reliability Management Control Strategies in High-performance Multicores," Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI, pp. 311-316, 2010.
[16] ISCA Tutorial. Retrieved August 1, 2013, from http://research.cs.wisc.edu/gems/isca_tutorial.ppt
[17] AMBA Advanced eXtensible Interface (AXI) Protocol Specication. Retrieved July 23, 2013, from http://esca.korea.ac.kr/teaching/comp427_ES/AMBA/AMBA_v30_AXI_v10.pdf