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研究生:黃文斌
研究生(外文):Wong, Man Pan
論文名稱:以軌道指派為基礎的可繞度評估系統
論文名稱(外文):Track-Assignment-Based Routability Estimation
指導教授:王廷基
指導教授(外文):Wang, Ting-Chi
學位類別:碩士
校院名稱:國立清華大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:36
中文關鍵詞:軌道指派
外文關鍵詞:track assignment
相關次數:
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  • 點閱點閱:197
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  • 收藏至我的研究室書目清單書目收藏:0
於現代的VLSI layout design中,routability的評估變得越來越具有挑戰性。在這篇論文中提出一個新的track assignment方法,可利用global routing所提供的資訊來對routability進行更為精確的評估。這個方法首先利用greedy method來產生一個初步的結果,然後應用negotiation-based方式透過rip-up及re-assignment方法來改善結果。不同於之前的其他方法,在這篇論文中我們提出把local nets列入考慮範圍,並允許routing產生violations。在這種方式中,routing congestion的資訊不僅比global routing更為準確,而且也更接近於detailed routing。於實驗結果中可看出這篇論文能所提出有力的方法。
Routability estimation has become much more challenging for modern VLSI layout design. In this thesis a new approach for track assignment is presented, which utilizes global
routing information to estimate routability in a more accurate manner. It first uses a greedy method to generate an initial solution, and then applies a negotiation-based rip-up and re-assignment method to improve the result. Dierent from any prior work, the proposed approach takes local nets into account and allows the generation of routing
violations. In this way, the routing congestion information is not only more accurate than global routing but also closer to detailed routing. Experimental results are shown
to support the robustness of the proposed approach.
1 Introduction
2 Preliminaries and Problem Description
2.1 Local Net Extraction
2.2 Problem Formulation
2.3 Cost Metrics
2.3.1 Overlap Cost and Blockage Cost
2.3.2 Wire Length Cost
3 Initial Assignment
3.1 Assignment Order
3.2 Calculation of Wire Length Cost
3.3 Calculation of Overlap Cost and Blockage Cost
3.4 Overall Cost Function
4 Overlap Reduction
4.1 Rip-up Step
4.2 Re-assignment Step
4.3 History Cost
5 Experimental Results
5.1 Comparison between the Initial Assignment Stage and the Overlap Reduc-tion Stage
5.2 Comparison between a Prior Work and NTA
5.3 Iroute Ordering in Initial Assignment
5.4 Parallelism
5.5 Routability Estimation from Global Routing and Track Assignment
6 Conclusions and Future Work
[1] H. Shojaei, A. Davoodi, J. T. Linderoth, Congestion analysis for global routing via
integer programming, in Proc: ICCAD, pp. 256-262, 2011.
[2] W.-H. Liu, Y.-L. Li, C.-K. Koh, A fast maze-free routing congestion estimator with
hybrid unilateral monotonic routing, in Proc: ICCAD, pp. 713-719, 2012.
[3] W.-H. Liu, Y. Wei, C. Sze, C. J.Alpert, Z. Li, Y.-L. Li, N. Viswanathan, Routing
congestion estimation with real design constraints, in Proc: DAC, 2013.
[4] H. Shojaei, A. Davoodi, J. T. Linderoth, Planning for local net congestion in global
routing, in Proc: ISPD, pp. 85-92, 2013.
[5] W.-H. Liu, C.-K. Koh, Y.-L. Li, Case study for placement solutions in ispd11 and
dac12 routability-driven placement contests, in Proc: ISPD, pp. 114-119, 2013.
[6] V. Yutsis, I. S. Bustany, D. Chinnery, J. R. Shinner, W.-H. Liu, ISPD 2014 benchmarks
with sub-45nm technology rules for detailed-routing-driven placement, in Proc: ISPD,
pp. 161-168, 2014.
[7] S. Batterywala, N. Shenoy, W. Nicholls, H. Zhou, Track assignment: a desirable inter-
mediate step between global routing and detailed routing, in Proc: ICCAD, pp 59-66,
2002.
[8] R. Kay, R. A. Rutenbar, Wire packing - a strong formulation of crosstalk-aware chip-
level track/layer assignment with an ecient integer programming solution, in Proc:
ISPD, pp 61-68, 2000.
[9] D. Wu, J. Hut, M. Zhaoj, R. Mahapatra, Timing driven track routing considering
coupling capacitance, in Proc: ASP
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