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研究生:洪仕哲
研究生(外文):Hung, Shih-Che
論文名稱:展頻時脈產生器
論文名稱(外文):Spread Spectrum Clock Generator
指導教授:張慶元張慶元引用關係黃錫瑜黃錫瑜引用關係
指導教授(外文):Chang, Tsin-YuanHuang, Shi-Yu
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:102
語文別:中文
論文頁數:73
中文關鍵詞:展頻時脈產生器鎖相迴路電磁干擾三角積分調變
外文關鍵詞:EMIPLLSSCG
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電腦資料傳輸介面(SATA)近來已成為資料儲存硬碟間重要的傳輸介面,隨著傳輸時脈越快,電磁干擾(EMI)的問題日益嚴重。借由濾波、屏蔽與展頻時脈可抑制電磁干擾的程度。使用濾波與屏蔽技術會增加重量與面積,並不適用於可攜帶式產品中,因此基於調頻方式的展頻時脈技術為最簡單且有效的方法。展頻時脈技術在時脈中心頻率以調頻的方式,將集中在中心頻率的能量分散至頻譜上。展頻時脈可將時脈中的基頻與高次諧波項對系統所造成的電磁干擾降低。
本論文使用ΔΣ分數型頻率合成器,結合一無須額外時脈的數位三角波型產生器與半除數除頻器,實現一應用於Serial-ATA II 的展頻時脈產生器。本論文實現的半除數除頻器的方法,只需在傳統的可程式化整數除頻器外,額外加入一負緣觸發正反器以及相位結合電路即可,因此無須增加太多的功耗。由於半除數除頻器在ΔΣ調變器工作時具有較小的相位跳動,因此可抑制ΔΣ調變器所產生的量化雜訊。
本論文所實現的展頻時脈產生器使用台灣積體電路公司0.18µm 1P6M CMOS 製程設計與佈局,中心操作頻率為3GHz借由頻率30 KHz的內建三角波型產生器可達到下展4883ppm的展頻範圍。在3GHz展頻的情況下時脈產生器rms 抖動量為6.65ps,展頻後rms抖動量為6.94ps,展頻後對電磁干擾的抑制量約為13dB。展頻時脈產生器在1.8-V電壓操作下功率消耗為12mW,整體晶片面積為1090×1330µm^2。
The serial advanced technology attachment (SATA) is becoming an important technique for internal storage interconnection. As the clock becomes faster, the electromagnetic interference (EMI) issue is harmful. The level of EMI can be mitigated with the help of filters, shielding and spread spectrum clocking. Spread spectrum clocking technique, based on a frequency modulation, has been the simplest and effective way. The frequency modulation alters the center frequency of the clock and spreads the power of spectrum over a broader range. This approach reduces the fundamental clock frequency EMI, as well as the harmonic components of higher order, decreasing the EMI radiation of whole system.
A Spread Spectrum Clock Generator (SSCG) for Serial-ATA II is realized in this thesis by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable divider with little power consumption added. This Half-integer divider utilized a half division ration to have a small phase jump to reduce quantization noise.
The SSCG achieves an output clock of 3 GHz and 4883ppm down spread with a 30 KHz triangular waveform and been designed based on TSMC 0.18µm 1P6M CMOS process. The rms jitter of spread-spectrum clock is 6.94ps.The EMI reduction is 13dB.The power is 12mW under 1.8-V.The chip area is 1090×1330µm^2.

第一章 緒論 - 1 -
1.1背景簡介 - 1 -
1.2研究動機 - 2 -
1.3論文架構 - 2 -
第二章 展頻時脈產生器概論 - 3 -
2.1整數型鎖相迴路 - 4 -
2.2展頻技術分類 - 5 -
2.3非整數型鎖相迴路 - 6 -
2.3.1一階三角積分調變器 - 9 -
2.3.2高階三角積分調變器 - 13 -
2.4消除量化誤差的方法 - 17 -
2.4.1電流補償技術 - 17 -
2.4.2相位補償技術 - 19 -
2.4.3真實非整數除頻器 - 20 -
第三章 鎖相迴路模型 - 23 -
3.1連續時間線性模型分析(S-領域模型) - 24 -
3.2鎖相迴路相位雜訊分析 - 29 -
3.3離散模型線性分析(Z-領域模型) - 31 -
3.3.1非時變脈衝轉換法 - 31 -
3.2.2除頻器縮減取樣混疊現象 - 32 -
3.4 Verilog-A 行為模型模擬 - 32 -
第四章 展頻時脈產生器設計與模擬 - 33 -
4.1簡介 - 33 -
4.2電路架構 - 34 -
4.3電路模擬 - 40 -
4.3.1壓控震盪器 - 40 -
4.3.2相位頻率偵測器 - 46 -
4.3.3電荷泵 - 49 -
4.3.4半除數除頻器 - 52 -
4.3.5三角積分調變器 - 54 -
4.3.6三角波型產生器 - 55 -
4.4模擬結果 - 57 -
第五章 佈局與量測 - 60 -
5.1展頻時脈產生器電路佈局圖 - 60 -
5.2展頻時脈產生器之量測設置 - 61 -
5.3展頻時脈產生器之量測結果 - 62 -
第六章 結論與未來展望 - 69 -
6.1結論 - 69 -
6.2未來展望 - 69 -
第七章 參考文獻 - 70 -


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