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研究生:李璧任
研究生(外文):Bi-Ren Lee
論文名稱:應用於低功率內嵌式動態隨機存取記憶體之溫度察覺自我刷新控制方案
論文名稱(外文):A Temperature-Aware Self-Refresh Control Scheme for Low Power Embedded-DRAM
指導教授:張孟凡
指導教授(外文):Meng-Fan Chang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:88
中文關鍵詞:內嵌式動態隨機存取記憶體溫度察覺低功率
外文關鍵詞:embedded DRAMtemperature awarelow power
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由於成本效益比靜態隨機存取記憶體高以及隨機存取速度比快閃記憶體更為快速的優點,嵌入式動態隨機存取記憶體被廣泛應用於多數的電子產品當中。然而對於系統單晶片而言,持續上升的功率消耗是一個存在的大問題。因此低功率消耗的研究議題應該要被考慮到晶片設計當中。對於內嵌式動態隨機存取記憶體而言,利用傳統制訂的自我刷新週期是為了要確保已經寫入的資料能夠被完整地保存於記憶胞陣列當中。但也因此當處於室溫狀況的時候,記憶胞的資料保存時間將可以比高溫環境下的保存時間還要能夠延伸至更久。因此在室溫的情況下,利用傳統的自我刷新週期將會有額外的資料保存功率消耗。
為了能夠降低在較為低溫狀況時的資料保存功率消耗,前人提出了溫度察覺自我刷新方案有效地去延長資料保存週期。但是此方法在製程變異之下會發生跳碼的危機,造成除頻的偵測無法完全執行,因此我們提出跳碼偵測電路,以防止此狀況發生,使電路可以完全偵測溫度進而決定刷新頻率。
在此方案中,我們的偵測電路與六十五奈米內嵌式動態隨機存取記憶體且低漏電的製程技術和一個由八百萬字元(8Mb)所組成的內嵌式動態隨機存取記憶體電路建構在一起。量測結果顯示對於資料保存功率損耗的交流部分,於室溫下的環境下可以節省高達百分之九十八點六二的功率損耗。
Embedded SRAM macros are widely used to System-On-Chip (SOC) memory because of their higher random access and lower cost per bit. However, increasingly large power consumption is a big problem in SOC system. For this reason, low power design issue should be taken into consideration. For embedded-DRAM, the stored data should be refreshed periodically in self-refresh mode. But at room temperature, the cell data retention time will extend much longer than that in higher temperature condition. Thus, there is an additional AC component of data refresh power at room temperature with conventional period.
In the previous work, the scheme of temperature-aware self-refresh (TASFR) control scheme is presented to extend self-refresh period in lower temperature condition. There bubble code effect in the TASFR control scheme, so we proposed a bubble code detector to prevent it in order to completely extend refresh period at room temperature.
We apply our design in 65nm eDRAM low leakage process within an 8Mb embedded DRAM macro. The experiment results show that, 98.62% reduction of AC component of data retention power can achieve at room temperature.
Chapter 1 Memory introduce
1.1 Low power embedded-DRAM applications
1.2 Challenges of low power embedded DRAM
1.3 Organization of thesis
Chapter 2 Characteristic of embedded DRAM
2.1 Embedded DRAM description
2.2 Embedded DRAM operation
2.2.1 Sense-Amplifier (SA)
2.2.2 Read operation
2.2.3 Write operation
2.2.4 Refresh operation
2.3 Embedded DRAM interface
2.3.1 DRAM-like interface
2.2.2 SRAM-like interface
Chapter 3 Design issue in low power self refresh mode
3.1 Cell structure 14
3.1.1 Trench-type capacitor
3.1.2 Stacked-type capacitor
3.1.2 Gain cell
3.2 Data retention time
3.2.1 Sub-threshold Current (I1)
3.2.2 Gate-Induced Drain Leakage (I2)
3.2.3 Gate-Oxide Tunneling Current (I3)
3.2.4 Hot carrier injection Current (I4)
3.2.5 Reverse-Biased Junction BTBT Current (I5)
3.2.6 Punch-Through Current (I6)
3.3 Power consumption
Chapter 4 Pervious scheme
4.1 Conventional self-refresh mode
4.1.1 One refresh-frequency
4.1.2 Temperature compensated self refresh (TCSR)
4.1.3 Partial array self refresh (PASR)
4.2 Temperature Dependency
4.2.1 Temperature Dependency in Self-Refresh Mode
4.2.2 Retention Time with Temperature Dependency
4.2.3 Power Dissipation with Temperature Dependency
4.3 Temperature-aware scheme
4.3.1 Replica-cell leakage monitoring scheme
4.3.2 Temperature Sensor
4.3.3 TASFU scheme
Chapter 5 Proposed scheme
5.1 Motivation
5.1.1 Process variations
5.1.2 Threshold voltage variation
5.1.3 Resister variation
5.2 Design consideration
5.2.1 Sense amplifier
5.2.2 Bubble code detector
5.3 Analyses of Proposed detector base on the TASFR Control Scheme
5.3.1 Adaptive refresh frequency
5.3.2 Power reduction in self-refresh mode
5.4 IAC comparison
Chapter 6 Embedded DRAM macro implementation
6.1 Marco implementation
6.1.1 Memory array structure
6.1.2 Peripheral circuit structure
6.1.3 I/O interface structure
6.2 Test chip
6.3 Layout shot
Chapter 7 Experimental results and conclusions
7.1 Measurement results
7.2 Measurement table
7.3 Measurement power
7.4 Comparison table and Conclusions
7.5 Future works
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