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研究生:紀俊全
研究生(外文):Chi, Chun-Chuan
論文名稱:三維積體電路的可測性架構以及連接導線瑕疵的診斷與修復方法
論文名稱(外文):DfT Architecture and Interconnect Defect Diagnosis and Repair for Interposer-Based 3D-ICs
指導教授:吳誠文
指導教授(外文):Wu, Cheng-Wen
學位類別:博士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:107
中文關鍵詞:2.5維積體電路3維積體電路可測性設計中介矽基底堆疊後測試測試存取機制穿矽孔瑕疵診斷連接導線自我測試連接導線修復良率提升
外文關鍵詞:2.5D-IC3D-ICDfTinterposerpost-bond testTAMTSVdefect diagnosisinterconnect BISTinterconnect repairyield enhancement
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穿矽孔 (Through-Silicon Via) 是一種矽晶片 (silicon die) 之間的垂直導線,這種技術使得晶片之間能夠有更多的連接線數目。利用穿矽孔,我們可以將多個矽晶片整合堆疊成一個三維積體電路 (3D-IC),三維積體電路比起傳統的二維積體電路能提供更好的效能以及更低的功率消耗,甚至更高的良率 (yield)。目前的實務上,一種製作三維積體電路的方法是將多個晶片彼此相鄰的堆疊在一個中介矽基底 (silicon interposer base) 上,在此中介矽基底上有金屬導線以及穿矽孔用來做為連接線。這種基礎於中介矽基底的三維積體電路製作方法又被稱為2.5維整合 (2.5D integration),因為每一個晶片上並沒有穿矽孔作為垂直連接線,穿矽孔只存在於中介矽基底上。
在本論文中,我們針對基礎於中介矽基底的三維積體電路,提出了一個可測性 (Design for Test) 架構以及一個測試策略,使得我們可以執行堆疊後 (post-bond) 測試。在晶片與中介矽基底堆疊黏合成一體之後,我們提出的可測性架構能夠用來測試三維積體電路外部的連接線,也能用來測試積體電路內部的每一個晶片。我們在論文中介紹了幾種不同的平行測試存取機制 (Parallel Test Access Mechanism),使用這些架構執行測試能夠縮短積體電路的測試時間。我們利用三維積體電路裡原本就存在的連接線以及封裝針腳來建構平行測試存取機制,使得所需要的成本能降到最低。對於每一種平行測試存取機制,我們提出了相對應的演算法,可以找到它們最佳的配置,使測試時間最短。我們另外也提出了一個增加測試專用連接線的方法,藉由在特定的位置增加連接線來增加測試頻寬,進一步再縮短測試所需的時間,此方法的代價就是額外的連接線所帶來的額外面積。實驗結果顯示,我們提出的測試策略在縮短測試時間上非常有效率。此外,我們進行了成本分析,結果顯示,我們提出的方法雖然會帶來額外成本,但是由於測試時間能夠大幅縮短,因此整體而言能夠有效降低總成本。
影響三維積體電路良率的其中一個重要原因是其連接線的健全性,因此在本論文中我們提出了一種連接線備援架構以及測試與修復方法,具有以下的特點。1. 偵測有錯誤的三維積體電路連接線。2. 當有斷路瑕疵存在時,指出斷路出現在連接線的哪一個位置,提升瑕疵診斷的解析度。3. 修復因為斷路瑕疵而發生錯誤的連接線以提升整體三維積體電路的良率。我們另外提出了一個連接線自我測試 (Built-In Self-Test) 電路,它可以執行全速 (at-speed) 連接線測試,偵測跟速度有關的連接線錯誤,提升測試品質。實驗結果顯示,在不同的瑕疵種類比例以及中介矽基底良率下,我們提出的連接線修復方法可以提升三維積體電路整體良率0%到13%。當斷路瑕疵佔大部分或者中介矽基底良率較低時,得到的三維積體電路良率提升會較高。由實作結果得知,我們提出的連接線自我測試電路所需要的額外面積很小。此外,成本分析顯示,雖然採用我們提出的連接線修復技術會需要額外的成本,但是由於良率能夠提升,因此最後能獲得的淨利是比不採用連接線修復技術更多的。
Through-Silicon Vias (TSVs) are high-density vertical interconnects between dies and they enable the creation of three-dimensional Integrated Circuits (3D-ICs) having higher performance and lower power consumption than traditional 2D-ICs. Currently, a practical TSV-based 3D integration approach is to place multiple dies (or die stacks) side-by-side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects; this is also referred to as 2.5D integration. In this thesis, we propose a Design-for-Test (DfT) architecture and a test strategy for post-bond testing of such interposer-based 3D-ICs. The architecture enables testing of external interconnects and die-internal circuits after dies and interposer are bonded together. We present various parallel (multi-bit) Test Access Mechanism (TAM) architectures, which aim to achieve short test times. Functional interconnects and package pins are reused to build the parallel TAM to minimize the test cost. For different TAM architectures, we propose corresponding optimization algorithms to help identify the best TAM configuration with the shortest test time. We also propose an “adding-wire” approach that can further reduce test time at the expense of extra test-dedicated interconnects between dies. Experimental results show that the proposed techniques are effective in test time reduction. Moreover, cost analysis is conducted and the results suggest that our approaches have lower costs compared with a base-case one-bit JTAG-only solution.
One of the most important factors that affect the yield of interposer-based 3D-ICs is the integrity of interconnects which connect various dies. Therefore, the second part of this thesis focuses on 3D-IC interconnect testing, diagnosis, and repair. We propose an interconnect redundancy architecture and a methodology for 1) detecting faulty 3D-IC interconnects, 2) identifying open defect locations within interconnects to improve defect diagnosis resolution, and 3) repairing the open interconnects to improve yield. We also propose a Built-In Self-Test (BIST) scheme which can improve test quality by enabling at-speed interconnect testing. Experimental results show that the 3D-IC yield gain achieved by the proposed interconnect repair scheme ranges from 0% to 13%, depending on different open defect ratio and interposer yield. For higher open defect ratio and lower interposer yield, the yield gain is higher. The area cost of the proposed BIST design is small. In addition, cost analysis results suggest that although the proposed interconnect repair approach induces extra costs, the net profit is higher than that without repair.
CHAPTER 1 Introduction 1
1.1 Through Silicon Vias 1
1.2 Three-Dimensional ICs 2
1.3 Test Challenges of 3D-ICs 4
1.4 Achievements of This Thesis 7
1.5 Organization of This Thesis 8
CHAPTER 2 DIE-LEVEL DFT CIRCUITRY 10
2.1 IEEE Std. 1149.1-Based Die Wrapper 10
2.2 IEEE Std. 1500-Based Die Wrapper 13
CHAPTER 3 POST-BOND TEST STRATEGY FOR 3D-ICS 18
3.1 Silicon Interposer Model 18
3.2 DfT Architecture and Test Strategy 20
CHAPTER 4 PARALLEL TAM OPTIMIZATION 24
4.1 Distribution TAM 24
4.2 Daisychain TAM 25
4.3 Hybrid TAM 31
4.4 Multi-Visit TAM 36
4.5 Adding Extra Interconnects to Improve TAM Width 40
4.6 Cost Analysis of Various TAM Optimization Approaches 49
CHAPTER 5 EXPERIMENTAL RESULTS ON TAM OPTIMIZATION 51
5.1 Experiment Setup 51
5.2 Success Rate 54
5.3 Test Time 58
5.4 Computing Time 60
5.5 Cost and Benefit 61
CHAPTER 6 3D-IC INTERCONNECT TEST, DIAGNOSIS, AND REPAIR 66
6.1 Interconnect Redundancy Architecture 66
6.2 Proposed Diagnosis and Repair Methodology 68
6.3 At-Speed Interconnect Testing by BIST 73
6.4 3D-IC Test and Repair Flow 79
6.5 Cost Analysis of the Proposed Interconnect Repair Scheme 81
CHAPTER 7 EXPERIMENTAL RESULTS ON INTERCONNECT REPAIR 85
7.1 Experiment Setup 85
7.2 3D-IC Yield Gain 86
7.3 Interconnect BIST Implementation 91
7.4 Cost and Benefit 93
CHAPTER 8 CONCLUSION AND FUTURE WORK 97
8.1 Parallel TAM Optimization 97
8.2 3D-IC Interconnect Test, Diagnosis, and Repair Scheme 98
8.3 Future Work 98
REFERENCES 100
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