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研究生:賴昶銘
研究生(外文):Lai, Chang-Ming
論文名稱:直接取樣寬頻雷達系統 於CMOS製程中
論文名稱(外文):A direct sampling boradband radar system in CMOS technology
指導教授:黃柏鈞黃柏鈞引用關係朱大舜
指導教授(外文):Huang, Po-ChiunChu, Ta-Shun
學位類別:博士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:147
中文關鍵詞:雷達脈衝直接取樣
外文關鍵詞:radarimpulsedirect-sampling
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雷達系統已經被廣泛的使用在影像及感測的應用裡,利用電磁波作為偵測媒介,藉此,雷達可以穿透非金屬物質,同時雷達的靈敏度並不會受到嚴苛環境的影響,這些獨特的特色使得雷達與可見光偵測成為了互補的技術,因此,在生醫、行車以及保全的應用上,雷達也逐漸成為了不可或缺的腳色,雖然雷達技術已經發展了數十年,在CMOS製程中,實現高度整合的雷達系統仍然相當罕見,在這個博士論文中,提出並實現了兩個脈衝雷達系統於CMOS中。

第一個晶片為可擴充直接取樣寬頻脈衝雷達,並且支援數位同時多角度陣列,這個雷達晶片具有一個發射機與一個直接取樣接收機,擁有距離偵測的能力,除此之外、數個晶片可以互相合作組成一個雷達系統已偵測角度,這些接收機可以重建反射波型於數位中,因此可以在數位中進行延遲與加總,在數位中,放大、複製與加總可以被無失真的執行,數位的平行陣列處理使得雷達可以同時多角度偵測,藉此以提升雷達的吞吐量,各個雷達單元之間的取樣時間必須同步並且獨立的控制,晶片上的數位時間轉換器藉由一個10 MHz 的信號源同步,數位時間轉換器採用了兩個步驟的時間產生方式,在100 ns的時間範圍中提供了6.35 ps 的解析度,等效上提供了15公尺範圍中0.94 mm的距離解析度,接收機射頻輸入端的10 dB 頻寬為12.7 GHz。最高等效位元數為6.4位元,所提出的架構實現在65-nm的CMOS製程中,晶片面積為1.3 x 1.4 mm2,在1V的供應電壓中,總共的消耗功率為76 mW 。

第二個晶片展示了一個寬頻脈衝時間陣列雷達,並且採用了時間平移直接取樣的架構,在發射機端與接收機端的取樣時間差決定了抵達時間的偵測,四個單元的時間陣列使得雷達系統具有波束成型的能力,不同通道間的時間差則是決定了接收機所偵測的角度,發射機的通道間一樣可以具有不同的時間差,以增強空間選擇的能力,這個直接取樣接收機可以將反射波形重建在數位中,使得數位信號處理可以充分利用這一些資訊,晶片上的數位時間轉換器提供了所需要的時序,並且具有高的解析度與寬的時間平移範圍,所提出的架構具有距離與角度的解析度分別為0.75 公分與3 度,發射機可以在800 ps中使用了10GS/s的取樣率合成各種不同的脈衝,接收機則具有20GS/s 的等效取樣率,所支援的射頻頻寬為2 4GHz,提出的設計實現在0.18 mm CMOS 中,使用的發射機與接收機晶片面積分別為5.4 3.3 mm2與5.4 5.8 mm2。
Radar systems are widely used in wireless imaging and sensing applications. Microwave radio is a detecting media that is capable of penetrating non-metallic materials, and radar sensitivity is not degraded even in severe weather conditions. These unique fea- tures make radar complementary to visible light-based detection. Therefore, radar gradually shows its essential rule in biometric, vehicular, and security applications. Though radar has been devel- oped for decades, a highly integrated radar system in CMOS is still rare. In this dissertation, two impulse radar systems are proposed and implemented in CMOS.

The first chip demonstrates a scalable direct-sampling broadband radar receiver supporting simultaneous digital multi beam array. The chip contains one transmitter and one direct-sampling receiver, which is capable of range estimation. Multiple chips can coop- eratively function as a radar system for azimuth detection. The receivers can reconstruct the scattered waveform into digital such that digital delay-and-sum can be performed. Amplification, du- plication and summation are executed in digital without distor- tion. Parallel array processing in digital is possible to perform si- multaneous multi beam, which enhances the throughput of radar. The sampling time of the receiver elements must be synchronized and controlled independently. The on-chip digital-to-time convert- ers (DTCs) are triggered by a 10-MHz reference source for synchro- nization. The two-step time generation in DTC provides a 6.25-ps resolution over a 100-ns range which is equivalent to a range reso- lution of 0.94 mm over a 15-m range. The receiver has an RF input 10-dB bandwidth of 12.7 GHz with maximal ENOB of 6.4 bit. The proposed architecture is implemented in 65-nm CMOS technology with silicon area of 1.3 × 1.4 mm2. The power consumption is 76 mW under a supply voltage of 1 V.

The second chip presents a broadband impulse radio timed-array radar utilizing a time-shifted direct-sampling architecture. Time shift between the sampling time of the transmitter and the receiver determines the time of arrival (TOA), and a four-element timed array enables beamforming. The different time shifts among the channels at the receiver determine the object’s direction of arrival (DOA). Transmitter channels have different shifts, as well, to en- hance spatial selectivity. The direct-sampling receiver reconstructs the scattered waveform in the digital domain, which provides full freedom to the backend digital signal processing. The on-chip DTC provides all the necessary timing with a fine resolution and wide shift range. The proposed architecture has a range and azimuth resolution of 0.75 cm and 3 degrees, respectively. The transmitter is capable of synthesizing a variety of pulses within 800 ps at a sampling rate of 10 GS/s. The receiver has an equivalent sampling frequency of 20 GS/s while supporting the RF bandwidth from 2 to 4 GHz. The proposed designs were fabricated in a 0.18-µm standard CMOS technology with a die size of 5.4 × 3.3 mm2 and 5.4 × 5.8 mm2 for the transmitter and the receiver, respectively.
List of Tables xv
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Impulse Radar Systems 5
2.1 Range Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 Frequency-Modulated Continuous Wave Radar . . . . . 6
2.1.2 Doppler Radar . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.3 Impulse Radar . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Azimuth Detection of Impulse Radar . . . . . . . . . . . . . . . 10
2.2.1 Antenna Spacing of Timed Array . . . . . . . . . . . . . 13
2.2.2 Element Number of Timed Array . . . . . . . . . . . . . 14
2.2.3 Transmitted Waveform Duration of Timed Array . . . . 14
3 System Consideration 19
3.1 TOA Detection in the Radar Receiver . . . . . . . . . . . . . . . 19
3.2 Equivalent Time Sampling . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Detection and SNR . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Link Budget in Impulse Radar System . . . . . . . . . . . . . . . 27
4 Scalable Direct-Sampling Radar Receiver Supporting Simultaneous
Digital Multi Beam 35
4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.1 Transmitter Circuits . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 Receiver Circuits . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.3 Digital to Time Converter . . . . . . . . . . . . . . . . . . 49
4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 52
5 Direct Sampling Radar System with 16 Time-Interleaving Path 69
5.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.1.1 DOA Detection in the Radar Receiver . . . . . . . . . . . 69
5.1.2 Timing Control for DOA and TOA . . . . . . . . . . . . . 75
5.2 Architecture of the Proposed Radar Array . . . . . . . . . . . . 79
5.2.1 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2.3 Digital-to-Time Converter . . . . . . . . . . . . . . . . . . 86
5.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.1 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.3.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.3 Digital-to-Time Converter . . . . . . . . . . . . . . . . . . 98
5.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . 100
6 Conclusion and Future Work 117
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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