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研究生:吳忠達
研究生(外文):Wu, Chung-Da
論文名稱:利用繞徑緩衝更有效率實現分離式分配機制
論文名稱(外文):A More Efficient Use of Separable Allocator With Bypass Buffer
指導教授:許雅三
指導教授(外文):Hsu, Yarsun
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:40
中文關鍵詞:單晶片網路分離式分配
外文關鍵詞:Network on Chipseparable allocator
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隨著製程的進步,單晶片系統中更多的運算單元使得一個具備可靠且可擴充性的連結網路變得至關重要,而單晶片網路(Network on Chip)因符合以上需求故逐漸成為趨勢。在網路中由於所含的路由器數量眾多,因此每個路由器中分配器(allocator)的運作效率將很大程度地影響封包所需的傳輸時間。分離式分配器(separable allocator)由於構造簡單等優點而成為分配器的一種常見選擇,但其簡單的分配機制也因此犧牲了其分配效率。為解決此問題,本篇研究提出了繞徑緩衝(bypass buffer)架構作為可能的解決方法。此架構做為分離式分配器的輔助硬體,可有效利用因低分配效率而閒置的路由器輸入與輸出埠,進而縮短封包所需的傳輸時間,並提升網路的整體效能。藉由模擬器的模擬結果可發現當路由器中每個埠所含的虛通道(virtual channel)數量越多,或封包在網路中的傳輸分佈越是平均,此架構最可完全發揮其功用,而最大地提升網路傳輸效率。
As more processors are integrated into a single chip, a robust interconnection network between them is becoming more important consequently. Allocator, a critical component in a router, plays a key role in determining which flit would be delivered forward through crossbar switch. An efficient allocator can achieve better matching quality in each cycle, and thus more flits are capable of being transmitted to their downward routers. As one kind of allocator, separable allocator is a common choice for its simple structure and low cost. However, its simple operation inevitably leads to lower matching quality. To address this problem, bypass buffer is therefore introduced in this research to enhance the utilization of the unused ports induced by the inefficiency of separable allocator. According to the performance and cost evaluation by simulation tools, a design with bypass buffer will get most benefit and bring less cost percentage when there are more virtual channels in a router. Moreover, the more balanced a traffic pattern is, the more bypass buffer could be utilized. Since the increased cost percentage brought about by bypass buffer varies considerably between different router architectures, whether to use bypass buffer would largely depend on the router configuration. As bypass buffer could not improve packet latency at low injection rate, using bypass buffer in a throughput-oriented network is more appropriate than in a latency-oriented network.
Chapter 1 Introduction 1
Chapter 2 Related Work 4
2.1 Allocation 4
2.2 Separable Allocator 7
2.3 The Pros and Cons of Separable Allocator 9
Chapter 3 Bypass Buffer 11
3.1 Architecture 11
3.2 Operation 13
3.3 Pipelining 15
3.4 Restrictions 15
Chapter 4 Performance Evaluation 20
4.1 Simulation Methodology 20
4.2 Traffic Patterns 22
4.3 The Size of Packet 25
4.4 The Number of Virtual Channels 27
4.5 The Depth of Bypass Buffer Queue 28
Chapter 5 Cost Evaluation 30
5.1 Simulation Setup 30
5.2 Area 31
5.3 Leakage Power 31
5.4 Dynamic Power 32
Chapter 6 Conclusions and Future Work 35
6.1 Conclusions 35
6.2 Future Work 37

Bibliography 39

[1]L. Benini and G. de Micheli. Networks on Chip: A New Paradigm for Systems on Chip Design. In Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), 2002.
[2]W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Inteconnection Networks. In Proceedings of the 38th Conference on Design Automation (DAC-38), 2001.
[3]W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, San Francisco, CA, 2004.
[4]J. Duato, S. Yalamanchili, and Lionel Ni, Interconnection Networks: an Engineering Approach, Morgan Kaufmann Publishers Inc., 2002.
[5]Y. Tamir and H.-C. Chi. Symmetric Crossbar Arbiters for VLSI Communication Switches. IEEE Transactions on Parallel and Distributed Systems, 4(1), 1993.
[6]W. J. Dally. Virtual-Channel Flow Control. IEEE Transactions on Parallel and Distributed Systems, 3(2), 1992.
[7]D. U. Becker and W. J. Dally, “Allocator implementations for network-on-chip routers,” in Proc. Conf. High Perf. Comput Network. Storage Anal. , Nov. 2009, pp. 1–12.
[8]T. Anderson, S. Owicki, J. Saxe, and C. Thacker, “High speed switch scheduling for local area networks,” ACM Trans. Comput. Syst., vol. 11, no. 4, pp. 319–352, Nov. 1993.
[9]J. G. Delgado-Frias and G. B. Ratanpal. A VLSI Wrapped Wave Front Arbiter for Crossbar Switches. In Proceedings of the 11th Great Lakes Symposium on VLSI, 2001.
[10]. Jiang, D. U. Becker, G. Michelogiannakis, J. Balfour, B. Towles, J. Kim, and W. J. Dally, “A Detailed and Flexible Cycle-Accurate Network-on-Chip Simulator,” in ISPASS’13.
[11]C. Sun, C.-H. O. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh, and V. Stojanovic, “DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Net-works-on-Chip Modeling,” in Proc. NOCS, 2012.
[12]Daniel H. Linder and Jim C. Harden. “An adaptive and fault tolerant wormhole routing strategy for k-ary n-cubes.” IEEE Transactions on Computers, 40(1):2–12, Jan. 1991.

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