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研究生:黃紹緯
研究生(外文):Shao-Wei Huang
論文名稱:使用0.18-μm互補式金氧半製程之鎖相迴路與頻率合成器之設計與實現
論文名稱(外文):Design and Implementation of Phase-Locked Loop and Frequency Synthesizer in Standard 0.18-μm CMOS Technology
指導教授:蔡政翰蔡政翰引用關係
指導教授(外文):Jeng-Han Tsai
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:應用電子科技學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:137
中文關鍵詞:鎖相迴路頻率合成器交叉耦合對電壓控制振盪器多模除頻器CMOSX頻段低功耗
外文關鍵詞:Phase-locked loopFrequency SynthesizerCross-coupled pair VCOMulti-Modulus DividerCMOSX-bandlow power
相關次數:
  • 被引用被引用:3
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對於各類通訊系統而言,隨著操作頻率越來越高,鎖相迴路也在其扮演著越來越重要的角色,而為了適應不同通訊系統規格的應用,鎖相迴路所要求的電路規格也有所不同,但還是會以低功耗與低相位雜訊為主要目標,只是這些目標還有許多問題需要克服,因此如何在各種電路特性上做取捨是最重要的議題。
在第四章實現了應用於5 GHz的鎖相迴路,其使用變壓器回授的壓控振盪器與高速的TSPC除頻器,讓鎖相迴路能達成低功耗與降低相位雜訊的目標。此外我們在振盪器中增置一組變容器來提高電路的調變範圍,而量測的相位雜訊在正常偏壓下,載波偏移100 kHz處為-88.15 dBc/Hz;在載波偏移10 MHz處為-117.89 dBc/Hz,整體功率消耗為26.5 mW,若在低偏壓下,載波偏移100 kHz處為-90.88 dBc/Hz;在載波偏移10 MHz處為-115.8 dBc/Hz,整體功率消耗為12.12 mW,操作範圍為4.33~5.1 GHz。
第五章實現了應用於X頻段的頻率合成器,其使用交叉耦合對的LC振盪器架構、電流模式邏輯除頻器與多模除頻器,來達成降低相位雜訊的目標。並且我們在LC振盪器中增置一組電容來提高共振腔中的品質因素,以提高電路相位雜訊的表現,此外在預除電路的部分的,我們將電流模式邏輯除頻器的尾電流源部分刪除以增加其操作速度。量測的相位雜訊在正常偏壓下,載波偏移100 kHz處為-67.28 dBc/Hz;載波偏移10 MHz處為-119.3 dBc/Hz,整體功率消耗30.26 mW,若在低偏壓下,載波偏移100 kHz處為-67.28 dBc/Hz;載波偏移10 MHz處為-119.3 dBc/Hz,整體功率消耗17.01 mW,操作範圍為10.43~10.77 GHz。

When the operating frequency becomes higher, high-speed frequency phase-locked loop plays more and more important roles in any type of communication systems. To satisfy various communication system standards, the circuit specifications are also dissimilar. In addition, the low power consumption and low phase noise are still the main goals. To overcome above issue, a good tradeoff between circuit architectures and performances has to be made.
In chapter four, a 5 GHz phase-locked loop has been designed and implemented. Utilizing the transformer feed-back VCO (voltage-controlled oscillator, VCO) and high-speed TSPC (true single phase clock, TSPC) divider, the PLL achieves low power consumption and low phase noise. To improve the circuit tuning range, we add a supernumerary varactor in VCO structure. When output frequency in 5 GHz, the measured phase noise are -88.15 dBc/Hz and -117.89 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 26.5 mW. The measured phase noise for low power consumption mode are -90.88 dBc/Hz and -115.8 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 12.12 mW. The operating frequency range is from 4.33 to 5.1 GHz.
In chapter five, a X-band frequency synthesizer has been developed. The cross-coupled pair LC VCO, current mode logic divider, and multi-modulus divider is adopted in the synthesizer design. In addition, to improve the circuit phase noise performance, a supernumerary capacitance is added to raise the quality factor of LC tank of the VCO. To promote the operating speed of the prescaler, we remove tail-current from CML (current-mode logic, CML) divider. When output frequency at 10.6 GHz, the measured phase noise are -67.28 dBc/Hz, –82.07 dBc/Hz and -119.36 dBc/Hz at 100 kHz, 1 MHz and 10 MHz frequency offsets, respectively. Total power consumption is 30.26 mW. The measured phase noise for low power consumption mode are -70.83 dBc/Hz and -121.71 dBc/Hz at 100 kHz and 10 MHz frequency offsets, respectively. Total power consumption is 17.01 mW. The circuit operating frequency range is from 10.43 to 10.77 GHz.

第一章 緒論 1
1.1 研究背景與動機 1
1.2 5 GHZ與X頻帶相關應用與介紹 2
1.3 文獻探討 2
1.4 論文架構 5
第二章 頻率合成器系統介紹 7
2.1 鎖相迴路介紹 7
2.2 鎖相迴路設計重點 8
2.3 鎖相迴路雜訊分析 11
2.4 鎖相迴路系統分析 12
第三章 頻率合成器電路介紹 20
3.1 相位頻率偵測器(PHASE FREQUENCY DETECTOR, PFD) 20
3.2 充電泵(CHARGE PUMP, CP) 26
3.3 迴路濾波器(LOOP FILTER, LP) 32
3.4頻率除頻器(FREQUENCY DIVIDER, FD) 34
3.5 電壓控制振盪器(VOLTAGE CONTROL OSCILLATOR, VCO) 35
3.5.1 電壓控制振盪器簡介 36
3.5.2 壓控振盪器設計重點 37
3.5.3 電壓控制振盪器架構比較 39
3.5.4 LC振盪器分析 41
3.5.5 在LC壓控振盪器的被動元件 44
3.5.5.1電感(Inductance) 44
3.5.5.2 變容器(Varactor) 47
3.5.6 壓控振盪器設計步驟 51
3.6 相位雜訊(PHASE NOISE)定義 53
3.6.1 Lesson’s Law相位雜訊模型 54
第四章 應用於5 GHZ鎖相迴路之設計與實現 57
4.1 簡介 57
4.2 架構與電路設計 58
4.2.1 相位頻率偵測器 59
4.2.2 充電泵 61
4.2.3 三階低通濾波器 63
4.2.4 電壓控制振盪器 66
4.2.5 變壓器回授之壓控振盪器分析 68
4.2.6變壓器回授之電壓控制振盪器的模擬結果 70
4.2.7 振盪器中變壓器與變容器模擬 71
4.2.8 除頻器 74
4.2.9 除頻器模擬結果 77
4.3 應用於5 GHZ鎖相迴路模擬結果 79
4.3.1 鎖相迴路系統模擬 79
4.3.1 鎖相迴路雜訊模擬 82
4.4 應用於5 GHZ鎖相迴路的量測結果 84
4.5結果與討論 91
第五章 應用於X-頻段頻率合成器之設計與實現 94
5.1 簡介 94
5.2 架構與電路設計 95
5.2.1 相位頻率偵測器 96
5.2.2 充電泵 98
5.2.3 三階低通濾波器 99
5.2.4 電壓控制振盪器 101
5.2.5 除頻鍊 106
5.2.6 多模除頻器之架構 106
5.3 應用於X頻段頻率合成器模擬結果 110
5.3.1頻段頻率合成器系統模擬 110
5.3.2 頻率合成器雜訊模擬 113
5.4 應用於X頻段頻率合成器的量測結果 114
5.5結果與討論 122
第六章 結論 128
參考文獻 130
自傳 137
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