跳到主要內容

臺灣博碩士論文加值系統

(34.204.169.230) 您好!臺灣時間:2024/03/03 07:35
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:黃柏蒼
研究生(外文):Bor-Tsang Hwang
論文名稱:具適應性負載暫態響應提升技術的電流模式降壓型轉換器之設計與實現
論文名稱(外文):Design and Implementation of the Current Mode Buck Converter with Adaptive Load Transient Enhancement Techniques
指導教授:陳中平陳中平引用關係
口試委員:陳科宏陳耀銘林宗賢
口試日期:2013-11-22
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:102
語文別:英文
論文頁數:132
中文關鍵詞:降壓型轉換器電流模式控制暫態響應電流泵補償電路
外文關鍵詞:buck convertercurrent mode controltransient responsecurrent pumpcompensation circuit
相關次數:
  • 被引用被引用:0
  • 點閱點閱:355
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程的演進,信號擺幅以及供應電壓持續的降低。因此,今日的電壓調節器必需在負載變動時能做出快速的反應並且維持穩定的輸出電壓。傳統的電流模式降壓型轉換器,由於頻寬上的限制無法擁有快速的暫態響應。在本論文中我們提出兩個新的架構來改善這個問題。
在切換式轉換器中,由於電感的限制電流無法立即改變,因此有文獻提出使用輸出電流泵的方式,在暫態時來補償電感電流與輸出電流的落差。然而這個架構無法直接適用於電流模式降壓型轉換器上。在第一顆晶片中,我們針對這個架構進行修正,提出適應性雙電流泵的方式。由於輸出電流泵會影響到原本迴路的運作,我們使用另一電流泵去彌補這個方式對於補償電路上的影響。這個架構被實現於TSMC 0.35μm CMOS製程。量測結果顯示暫態響應的回復時間約為2.8~4 μs。相較於傳統架構而言,回復時間被減少了約75%。另外,在輸出電流介於120~600 mA間,轉換效率皆大於82 %;與傳統架構相比,這個架構所造成的效率衰減皆小於0.3%。
在第二顆晶片中,我們使用動態調整補償電路電壓的方式。在電流模式控制中,補償電容上的電壓需要隨不同負載而有所變動。因此,藉由將電感電流的資訊加到補償電路的輸出上,使得當不同負載時補償電容所需的電壓變動量較傳統架構減少,藉此來達到較快的反應速度。這個架構被實現於TSMC 0.25μm CMOS製程。佈局後模擬顯示其暫態響應的回復時間約為3~6 μs。而實現這個架構所需要增加的面積約為57.5k μm2,遠較前一個架構所需要增加的面積小(333k μm2)。另外,在輸出電流介於100~500 mA間,轉換效率皆大於90%;與傳統架構相比,這個架構所造成的效率衰減皆小於0.4%。

With the evolution of the process, the supply voltage and the signal level decreases. Therefore, fast load transient response to keep output voltage stable and clean becomes very critical for voltage regulators nowadays. Traditional current mode buck converter cannot attain fast transient response due to bandwidth limitations. In this thesis, we propose two new architectures to improve this problem.
The output current slew rate of switching converters is restricted by the inductor. Therefore, the additional current pump is proposed in the literature to provide the insufficient current between the inductor and the output load when loading is changed suddenly. However, this architecture cannot apply to the current mode buck converters directly. In the first chip, we modify this architecture and adopt the adaptive dual current pump technique. Since the output current pump will affect the operation of the original loop, the other current pump is added to make up its impact on the compensation circuit. This technique is implemented with TSMC 0.35μm CMOS process. Measurement results show the recovery time is within 2.8~4 μs. Compared with conventional design, the performance of recovery time is reduced by about 75%. In addition, power conversion efficiency is larger than 82% with load current between 120 mA and 600 mA in proposed architecture. Efficiency degradation is less than 0.3% compared with conventional architecture.
In the second chip, we use the dynamic voltage adjustment of the compensation circuit technique. In current mode control, the voltage of the compensation capacitor needs to be changed according to different load conditions. By adding the inductor current signal to the output of the compensation circuit, the voltage difference of the compensation capacitor at different loads can be reduced. As a result, faster transient response is obtained. This technique is implemented with TSMC 0.25μm CMOS process. Post-layout simulation results show the recovery time is within 3~6 μs. The additional area for implementing this technique is 57.5k μm2, which is much smaller than the previous technique (333k μm2). In addition, power conversion efficiency is larger than 90 % with load current between 100 mA and 500 mA in proposed architecture. Efficiency degradation is less than 0.4% compared with conventional architecture.

誌謝 i
摘要 iii
Abstract v
Contents vii
List of Figures xii
List of Tables xx
Chapter 1 Introduction 1
1.1 Background of Regulators 1
1.2 Classification of Voltage Regulators 2
1.2.1 Linear Regulators 2
1.2.2 Switching Capacitor Circuits 4
1.2.3 Switching Regulators 6
1.3 Design Motivation 9
1.4 Specification 11
1.5 Thesis Organization 12
Chapter 2 Fundamentals of DC-DC Buck Converter 13
2.1 General Specifications 13
2.1.1 Efficiency 13
2.1.2 Regulation 16
2.1.3 Transient Response 17
2.2 Operation of DC-DC Buck Converter 20
2.3 Ripple-Based and PWM Control Mechanism 27
2.4 Voltage-Mode and Current-Mode Buck Converter 30
2.4.1 Voltage Mode Buck Converter 31
2.4.2 Current Mode Buck Converter 33
Chapter 3 Adaptive Dual Current Pump Technique for Current Mode Buck Converters…… 37
3.1 Prior Works 37
3.1.1 Current Pump Technique 37
3.1.2 Dual Mode Control Technique 39
3.1.3 Gm-Enhancement Technique 41
3.1.4 Adaptive Pole-Zero Position Technique 42
3.2 Proposed Architecture 44
3.2.1 Analysis of Prior Works 44
3.2.2 Proposed Architecture 49
3.2.3 Behavior Model Simulation 51
3.3 Circuit Level Implementation 54
3.3.1 Flash ADC 54
3.3.2 Comparator with Preamplifier 55
3.3.3 Current Pump 58
3.3.4 Transconductance Amplifier 59
3.3.5 Comparator 61
3.3.6 Oscillator and Ramp Generator 64
3.3.7 Current Sensor 66
3.3.8 V-I Converter 68
3.3.9 Buffer and Dead-Time Control 70
3.3.10 Soft-Start 72
3.4 Layout &; Post-Layout Simulation 73
3.4.1 Layout 73
3.4.2 Post-Layout Simulation Results 74
3.5 Measurement 79
3.5.1 Chip Photo 79
3.5.2 Measurement Setup 79
3.5.3 Measurement Results 80
3.5.3 Comparison Table 86
3.6 Issues of this Chip 86
Chapter 4 Dynamic Voltage Adjustment of the Compensation Circuit for Current Mode Buck Converter 88
4.1 Proposed Architecture 88
4.1.1 Analysis of the Proposed Architecture 88
4.1.2 Stability Consideration 92
4.1.3 Behavior Model Simulation 95
4.2 Circuit Level Implementation 96
4.2.1 Modification of the Comparator with Reset Function 97
4.2.2 Modification of the Current Sensor with Negative Inductor Current Sensing 102
4.2.3 Sample and Delay Circuit 106
4.2.4 Auxiliary Gm Circuit 108
4.2.5 Decision Circuit 111
4.2.6 Dynamic Voltage Adjustment Circuit 113
4.2.7 Adaptive Resistance Circuit 114
4.3 Layout &; Post-layout Simulation 117
4.3.1 Layout 117
4.3.2 Post-Layout Simulation Results 117
4.3.3 Compared with Conventional Architecture 121
4.3.4 Comparison Table 123
Chapter 5 Conclusion and Future Works 124
5.1 Conclusion 124
5.2 Future Works 125
REFERENCES 126

[1]Y.-H. Lin, K.-L. Zheng, and K.-H. Chen, “Power MOSFET array for smooth pole tracking in LDO regulator compensation,” in Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), Aug. 2007, pp. 554-557.
[2]H.-J. Yang, H.-H. Huang, C.-L. Chen, M.-H. Huang, and K.-H. Chen, “Current feedback compensation (CFC) technique for adaptively adjusting the phase margin in capacitor-free LDO regulators,” in Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), Aug. 2008, pp. 5-8.
[3]C.-H. Lin, K.-H. Chen, and H.-W. Huang, “Low-dropout regulators with adaptive reference control and dynamic push-pull techniques for enhancing transient performance,” IEEE Trans. Power Electron., vol. 24, no. 4, pp. 1016-1022, Apr. 2009.
[4]M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007.
[5]P. Favrat, P. Deval and M. J. Declercq, “A high-efficiency CMOS voltage doubler,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 410-416, Mar. 1998.
[6]J. Starzyk, Y.-W. Jan, and F. Qiu, “A DC-DC charge pump design based on voltage doublers,” IEEE Trans. Circuits Syst. I: Fund. Theory and Appl., vol. 48, no. 3, pp. 350-359, Mar. 2001.
[7]C.-Y. Hsieh, P.-C. Fan, and K.-H. Chen, “A dual phase charge pump with compact size,” in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2007, pp. 202-205.
[8]Y.-K. Luo, K.-H. Chen, and W.-C. Hsu, “A dual-phase charge pump regulator with nano-ampere switched-capacitor CMOS voltage reference for achieving Low output ripples,” in Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sep. 2008, pp. 446-449.
[9]R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Trans. Power Electron., vol. 6, no. 2, pp. 271–280, Apr. 1991.
[10]F.-F. Ma, W.-Z. Chen, and J.-C. Wu, “A monolithic current-mode buck converter with advanced control and protection circuit,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1836–1846, Sep. 2007.
[11]C.-Y. Leung, P. K. T. Mok, and K.-N. Leung, “A 1-V integrated current mode boost converter in standard 3.3/5-V CMOS technologies,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2265–2274, Nov. 2005.
[12]D. Ma, W.-H. Ki, and C.-Y. Tsui, “A pseudo-CCM/DCM SIMO switching converter with freewheel switching,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1007–1014, Jun. 2003.
[13]C.-Y. Hsieh and K.-H. Chen, “Adaptive pole-zero position (APZP) technique of regulated power supply for improving SNR,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2949–2963, Nov. 2008.
[14]Maxim, “MAX8640Y/MAX8640Z data sheet: Tiny 500mA, 4MHz/2MHz synchronous step-down DC-DC converters,” Rev. 3, June 2008, Accessed on Dec. 3, 2008.
[15]C.-S. Wang, Y.-P. Su, Y.-H. Lee, C.-C. Lin, K.-H. Chen, and M.-J. Du, “Reduction of equivalent series inductor effect in delay-ripple reshaped constant on-time control for buck converter with multilayer ceramic capacitors,” IEEE Trans. Power Electron., vol. 28, no. 5, pp. 2366–2376, May 2013.
[16]B. Arbetter, R. W. Erickson, and D. Maksimovic, “DC-DC converter design for battery-operated systems,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), Jun. 1995, pp.103–109.
[17]R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed. Norwell, MA: Kluwer, 2001.
[18]R. Redl and J. Sun, “Ripple-based control of switching regulators—An overview,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2669–2680, Dec. 2009.
[19]S. Hsu, A. Brown, L. Rensink, and R. Middlebrook, “Modeling and analysis of switching dc-to-dc converters in constant frequency current programmed mode,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), Jun. 1979, pp. 284–301.
[20]P.-J. Liu, Y.-K. Lo, H.-J. Chiu, and Y.-J. Chen, “Dual-current pump module for transient improvement of step-down DC-DC converters,” IEEE Trans. Power Electron., vol. 24, no. 4, pp. 985–990, Apr. 2009.
[21]P.-J. Liu, W.-S. Ye, J.-N. Tai, H.-S. Chen, J.-H. Chen, and Y.-E. Chen, “A high-efficiency CMOS DC-DC converter with 9- μs transient recovery time,” IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp. 575 - 583, Mar. 2012.
[22]J. Roh, “High-performance error ampli&;#64257;er for fast transient DC-DC converters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 9, pp. 591–595, Sep. 2005.
[23]H.-W. Huang, H.-H. Ho, C.-C. Chien, K.-H. Chen, G.-K. Ma, and S.-Y. Kuo, “Fast transient DC-DC converter with on-chip compensated error ampli&;#64257;er,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2006, pp. 324–327.
[24]K.-H. Chen, H.-W. Huang, and S.-Y. Kuo, “Fast transient DC–DC converter with on-chip compensated error amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 12, pp. 1150–1154, Dec. 2007.
[25]C.-F. Lee and P. K. T. Mok, “A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique,” IEEE J. of Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004.
[26]R. Gregorian, Introduction to CMOS Op-Amps and Comparators. New York: Wiley, 1999.
[27]C.-Y. Leung, P. K. T. Mok, K.-N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator,” IEEE Trans. Circuits Syst. II, vol. 52, no. 7, pp. 394 - 397, Jul. 2005.
[28]N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics Converters, Applications, and Design, 3rd ed. New York: Wiley, 2003.
[29]K.-H. Chen, C.-J. Chang, and T.-H. Liu, “Bidirectional current-mode capacitor multipliers for on-chip compensation,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 180–188, Aug. 2008.
[30]Y.-H. Lee, S.-J. Wang, and K.-H. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitor,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 829–838, Apr. 2010.
[31]P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-Type III compensation,” IEEE J. of Solid-State Circuits, vol. 45, no. 8, pp. 1446-1455, Aug. 2010.
[32]Y.-H. Lee, S.-C. Huang, S.-W. Wang, and K.-H. Chen "Fast transient (FT) technique with adaptive phase margin (APM) for current mode DC-DC buck converters," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 10, pp. 1781 -1793, Oct. 2012.
[33]Y.-H. Lee, C.-C. Chiu, S.-Y. Peng, K.-H. Chen, Y.-H. Lin, C.-C. Lee, C.-C. Huang, and T.-Y. Tsai, “A near-optimum dynamic voltage scaling (DVS) in 65 nm energy-ef&;#64257;cient power management with frequency-based control (FBC) for SoC system,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2563-2575, Nov. 2012.
[34]J.-C. Tsai, C.-L. Chen, Y.-H. Lee, H.-Y. Yang, M.-S. Hsu, and K.-H. Chen "Modified hysteretic current control (MHCC) for improving transient response of boost converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 10, pp. 1967 -1979, Oct. 2011.
[35]H.-W. Huang, K.-H. Chen, and S.-Y. Kuo, “Dithering skip modulation, width and dead time controllers in highly ef&;#64257;cient DC-DC converters for system-on-chip applications,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2451–2465, Nov. 2007.
[36]V. Gutnik and A. P. Chandrakasan, “Embedded power supply for low power DSP,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 425–435, Dec. 1997.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊