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研究生:簡佑勛
研究生(外文):Yu-Hsun Chien
論文名稱:二百五十億位元每秒之光接收器電的設計與分析
論文名稱(外文):Design and Analysis of 25 Gb/s Optical Receivers
指導教授:劉深淵
指導教授(外文):Shen-Iuan Liu
口試委員:陳巍仁鄭國興汪重光林宗賢
口試日期:2014-01-21
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:49
中文關鍵詞:轉阻放大器限幅放大器雜訊抵消功率可調
外文關鍵詞:transimpedance amplifierlimiting amplifiernoise-cancelingpower scalable
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隨著眾多多媒體應用的快速成長,操作於每秒十幾億的高速收發器需要光纖作為傳輸媒介,因為其損耗低於同軸電纜。典型的前端接收器電&;#63799;包含&;#63930;一轉阻放大器以及一限幅放大器。轉阻放大器為&;#63930;達到低的位元錯誤&;#63841;必須維持低雜訊,而限幅放大器必須提供足夠高的增&;#64023;和頻寬去將幾毫伏特的電壓放到至幾百毫伏特。
此篇&;#63809;文主要分為&;#63864;個部分。在第二章中,提及使用雜訊抵消的轉阻放大器。&;#63976;面將有一個詳細的轉阻放大器之雜訊分析。此晶片由四十&;#63756;米互補式&;#63754;屬氧化物半導體製程製作。此放大器操作於&;#63864;百五十億位元每秒且提供68 dBΩ 的整體增&;#64023;。&;#63870;測的輸入積分雜訊為3.1μArms。在輸入為&;#63864;百五十億位元每秒之2的-7次方-1 的仿真隨機字&;#63749;序&;#63900;下,&;#63870;測得的位元錯誤&;#63841;小於10的-12次方。此接收器消耗由電源供應器提供的1.2 伏特、93.8 毫瓦。整體面積為0.64 平方公厘。
在第三章中將提及功&;#63841;可調的限幅放大器,&;#63976;面將會有一個限幅放大器&;#63851;&;#63849;設計&;#63946;程。此晶片使用四十&;#63756;米互補式&;#63754;屬氧化物半導體製程製作。此放大器操作於&;#63864;百五十億位元每秒且提供64 dBΩ 的整體增&;#64023;。&;#63870;測的輸入積分雜訊為2.7μArms。在輸入為&;#63864;百五十億位元每秒之2的7次方-1 的仿真隨機字&;#63749;序&;#63900;下,&;#63870;測得的位元錯誤&;#63841;小於10的-12次方。此接收器消耗由電源供應器提供的1.3 伏特、103 毫瓦。整體面積為1.16 平方公厘。

With the rapid growth of numerous multimedia applications, high-speed transceivers operating at tens of gigabits per second demand the optical fiber to be the media since optical fiber suffers less loss as coaxial cable does [1]. The typical front-end receiver consists of a TIA and a LA. The TIA must introduce low noise to achieve a low BER and the LA must provide an enough gain and bandwidth to amplify the signals from a few of millivolts to several hundreds of millivolts.
This thesis is manly divided into two parts. In chapter 2, the noise-canceling transimpedance amplifier is proposed. There is a detailed noise analysis of the TIA. The chip is fabricated in 40nm-CMOS process. Operating at 25 Gb/s, the amplifier provides an overall gain of 68dBΩ. The measured input integrated noise is 3.1μArms and measured BER is < 10^-12 for a 25 Gb/s PRBS of 2^7-1. Its power consumption is
93.8mW/ch from a 1.2V supply. The total area is 0.64mm^2.
In chapter 3, the power scalable limiting amplifier is proposed. A design methology of power scalable LA is introduced. The chip is fabricated in 40nm-CMOS process. Operating at 25 Gb/s, the amplifier provides an overall gain of 64dBΩ. The measured input integrated noise is 2.7μArms and measured BER is < 10-12 for a 25 Gb/s PRBS of 2^7-1. Its power consumption is 103mW/ch from a 1.3V supply. The
total area is 1.16mm^2.

1.Introduction…………………………………………………… 1
1.1 Optical Communication…………………. 1
1.2 Low Noise TIA……...…………………… 2
1.3 Limiting Amplifier……………………… 3

2. A 25 Gb/s Receiver with Noise-Canceling TIA 4
2.1 Motivation…………………………………………… 4
2.2Circuit Architecture…………………………… 5
2.2.1Circuit Description……………………………5
2.2.2Noise-Canceling TIA……………………………6
2.2.3Limiting Amplifier, S/D and OC……………12
2.2.4Simulation Result………………………………15
2.3Measurement Setup and Measurement Results…16
2.3.1 Measurement Setup…………………………… 16
2.3.2Measurement Results………………………… 17
2.4Die Photo and Performance Summary………… 20

3. A 3-25 Gb/s × 4-channel Receiver with Noise-Canceling TIA and Power Scalable LA 22
3.1Motivation……………………………………… 22
3.2Circuit Architecture………………………… 23
3.2.1Circuit Description………………………… 23
3.2.2Noise-Canceling TIA………………………… 25
3.2.3Power Scalable Limiting Amplifier……… 25
3.2.4Single-to-Differential Circuit and Offset Cancellation Circuit…………………………………………… 27
3.2.5Bit Rate Detection Circuit…………………30
3.2.6Simulation Result…………………………… 31
3.3Measurement Setup and Measurement Results…35
3.3.1Measurement Setup………………………………35
3.3.2Measurement Results……………………………36
3.4Die Photo and Performance Summary……………44

4. Conclusion and Future Work…………………………46
4.1Conclusion …………………………………………46
4.2Future Work…………………………………………47

Bibliography ……………………………………………………………48


[1]E. Sackinger, Broadband Circuits for Optical Fiber Communication. New York: Wiley Interscience, 2005.

[2]B. Razavi, Design of Integrated Circuits for Optical Communications, pp. 136–140, McGraw-Hill, New York, 2003.

[3]S. M. Park, H. J. Yoo, ”1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications”, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 112-121, Jan. 2004.

[4]F. Bruccoleri, E. A. M. Klumperink and B. Nauta, ”Wide-Band CMOS Low-Noise Amplifier Exploiting Thermal Noise Canceling”, IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 275-282, Feb. 2004.

[5]T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 1st ed., New York: Cambridge Univ. Press, 1998.

[6]M. Atef and H. Zimmermann, “2.5Gbit/s Transimpedance Amplifier Using Noise Cancelling for Optical Receivers,” IEEE ISCAS Symp. Dig., pp. 1740-1743, May 2012.

[7]J. S. Weiner et al., “An InGaAs-InP HBT Differential Transimpedance Amplifier with 47 GHz Bandwidth,” IEEE J. Solid-State Circuits, vol.
39, no. 10, pp. 1720–1723, Oct. 2004.

[8]J.-D. Jin and S. S. H. Hsu, "40 Gb/s Transimpedance Amplifier in 0.18-um CMOS Technology," IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1449-1457 , June 2008.

[9]C. Kromer, G. Sialm, T. Morf, M. Schmatz, F. Elliner, D.Erni, and H. Jackel, “A Low-Power 20-GHz 52-dBΩ Transimpedance Amplifier in 80-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885-894, June 2004.


[10]F. Aflatouni, and H. Hashemi, “A 1.8-mW Wideband 57dBΩ Transimpedance Amplifier in 0.13μm CMOS,” IEEE RFIC Symp. Dig., pp. 57-60, June 2009.

[11]S. Bashiri, C. Plett, J. Aguirre, and P. Schvan, “A 40 Gb/s Transimpedance Amplifier in 65nm CMOS,” IEEE ISCAS Symp. Dig., pp. 757-760, Aug. 2010.

[12]J. Kim and J. F. Buckwalter, “Bandwidth Enhancement with Low Group-Delay Variation for 40-Gb/s Transimpedance Amplifier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 1964–1972, Aug. 2010.

[13]C.-F. Liao and S.-I. Liu, “40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 642–655, Feb. 2008.

[14]J.-Y. Jiang, P.-C. Chiang, H.-W. Hung, C.-L. Lin, T. Yoon and J. Lee, “100Gb/s Ethernet Chipsets in 65nm CMOS Technology,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 120-121

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