臺灣博碩士論文加值系統

NAND型快閃記憶體已被廣泛應用在嵌入式系統和消費電子產品，由於它具有低功耗、快速存取、非揮發性、高抗震等特色。現今，SSD的架構大多採用多控制器架構來處理NAND型快閃記憶體晶片。在傳統多控制器的結構設計 (TMCD) 下，每一個控制器都各自處理自己匯流排上的NAND型快閃記憶體晶片。然而，在並行多控制器的結構設計 (PMCD) 下，任何的晶片將不再侷限於任何特定的控制器，每一個閒置的控制器能透過多控制器架構的設計去存取任何的晶片。在這篇論文中，我們將提出一個新的方法，有效的利用固態硬碟多控制器的平行處理能力。當快閃記憶體轉換層 (FTL) 使用了我們所提出的方法，實驗結果證明，執行時間減少高達5.52％。

NAND flash memory has been widely utilized in embedded systems and consumer electronics, because of its low-power consumption, high-performance access, non-volatility, and shock resistance. Nowadays, the architecture of SSD is using multiple controllers to handle NAND flash memory chips. Under the architecture of traditional multi-controller design (TMCD), one controller can only take responsibility for the specific NAND flash memory chips on its own bus; nevertheless, under the architecture of parallel multi-controller design (PMCD), any controllers can access any NAND flash memory chips on a SSD. In this thesis, we will propose a method to exploit multi-controller parallelism for solid-state drives regardless of TMCD or PMCD. When a flash translation layer (FTL), which provides a block device interface on top of flash memory, adopts the method, the experimental results show that the FTL for multi-controller design could reduce the total response time up to 5.52%.

Chapter 1 Introduction 2
Chapter 2 Background Knowledge 5
2.1 Related work 5
2.2 Solid-State Drive (SSD) 8
2.3 Flash Translation Layer (FTL) 10
Chapter 3 Problem Overview 14
3.1 Merge Operations of Hybrid-Mapped FTLs 14
3.1.1 Switch Merge 14
3.1.2 Partial Merge 15
3.1.3 Full merge 15
3.2 Motivation 17
Chapter 4 Exploiting Multi-controller Parallelism for Solid-State Drives 20
4.1 Overview 20
4.2 Handling read/write operations under TMCD and PMCD 22
4.3 Handling merge operations under TMCD and PMCD 28
4.3.1 Switch Merge 28
4.3.2 Partial Merge 29
4.3.3 Full merge 30
Chapter 5 Performance Evaluation 33
5.1 Environment setup and trace 33
5.2 Effect of Merge Operation 36
5.3 Overall performance 39
Chapter 6 Conclusion 42
References 44

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