(3.227.0.150) 您好!臺灣時間:2021/05/08 08:40
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:楊佳倫
研究生(外文):Jia-lun Yang
論文名稱:具有降低參考突波技巧的1伏特2.4 GHz分數型頻率合成器晶片設計
論文名稱(外文):A 1-V 2.4-GHz Fractional-N Frequency Synthesizer Chip Design with Reference Spur Reduction Techniques
指導教授:黃進芳黃進芳引用關係
指導教授(外文):Jhin-fang Huang
口試委員:黃進芳
口試委員(外文):Jhin-fang Huang
口試日期:2014-01-14
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:140
中文關鍵詞:鎖相迴路頻率合成器低參考頻率突波低相位雜訊
外文關鍵詞:phase-locked loopfrequency synthesizerlow reference spurlow phase noise
相關次數:
  • 被引用被引用:0
  • 點閱點閱:99
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:8
  • 收藏至我的研究室書目清單書目收藏:0
近年來,隨著無線通訊系統快速發展,各式各樣的頻率合成器被研發出來,通常傳統的鎖相迴路之迴路濾波器均使用連續時間被動式濾波器,其需要較大的電容值才能滿足系統的需求。且濾波器連接壓控振盪器的控制端點處,會有漣波效應的產生,常常需要在鎖定時間長短與參考頻率突波做取捨。
第一顆晶片,我們介紹了一個降低參考突波技巧的2.4 GHz分數型頻率合成器的架構。使用了離散時間取樣、保持、重置迴路濾波器,主要功用為隔離充電汞的輸出與VCO的控制電壓點,使PFD、CP有較好的線性度,其能達到低突波與低相位雜訊的性能,並節省使用較低迴路頻寬時,所造成的大電容面積。此頻率合成器是使用台積電所提供0.18微米CMOS製程以1伏特來完成晶片研製與量測,而量測結果顯示頻率範圍為2.21~2.52 GHz,其13.1%,頻率鎖定在2.4 GHz時,距離主頻1 MHz處的相位雜訊為-117.1 dBc/Hz,參考訊號突波高度為-65 dBc,功率消耗為15.2 mW,晶片面積含Pad後為1.06 mm2。
第二顆晶片,我們採用了次取樣充電汞與隨機選擇相位頻率偵測器來降低參考突波。此頻率合成器將電壓控制振盪器的控制端產生的漣波隨機化,這樣可使鎖相迴路輸出頻譜的參考頻率突波降低。次取樣充電汞也是用來減少控制端的漣波達到降低參考突波的效果。此頻率合成器是使用台積電所提供0.18微米CMOS製程以1伏特來完成晶片研製與量測,而量測結果顯示頻率範圍為2.235~2.579 GHz,其14.3%,頻率鎖定在2.41 GHz時,距離主頻1 MHz處的相位雜訊為-113.17 dBc/Hz,參考訊號突波高度為-70.4 dBc,功率消耗為9 mW,晶片面積含Pad後為0.695 mm2。
In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. Normally, the loop filter of a conventional PLL are using continuous-time passive loop filter, it needs a large capacitance to meet system requirements. And the control node of the VCO is directly connected to the loop filter that will introduce ripples. Usually deals with a tradeoff between the settling time and the magnitude of the reference sideband that appears at the PLL output.
The first chip, we introduce a 2.4 GHz fractional-N frequency synthesizer architecture with a reference spur reduction technique. It adopts a sample-hold-reset loop filter to isolate the charge pump output node and the VCO control node, which has a better linearity of PFD and CP. It achieves low spur and low phase noise performance, and save the capacitance area while a narrow loop bandwidth is used. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.21 GHz to 2.52 GHz corresponding to a frequency tuning range of 13.1%, a phase noise of -117.1 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -65 dBc, a power consumption of 15.2 mW and the with pads chip area is only 1.06 mm2.
The second chip, we adopt a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur. The frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. The SSCP circuit is also utilized to reduce ripples on the control voltage to achieve low spur level. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.235 GHz to 2.579 GHz corresponding to a frequency tuning range of 14.3%, a phase noise of -113.17 dBc/Hz at 1 MHz offset from 2.41 GHz, a reference spur of -70.4 dBc, a power consumption of 9 mW and the with pads chip area is only 0.695 mm2.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Focus and Contributions 2
1.3 Organization of This Thesis 2
Chapter 2 The Basics of Frequency Synthesizers 5
2.1 Wireless Transceiver 5
2.2 Phase-Locked Loop 6
2.2.1 Integer-N Frequency Synthesizer 7
2.2.2 Fractional-N Frequency synthesizer 8
2.3 General Considerations 9
2.3.1 Phase Noise 9
2.3.2 Spurs 11
2.3.3 Jitter 12
2.4 Frequency Synthesizer Paper Survey 13
2.7 Summary 24
Chapter 3 PLL Analysis and Circuit Design 25
3.1 Voltage-Controlled Oscillator Circuit (VCO) 25
3.1.1 General Operation Principles 26
3.1.2 Ring Oscillator Circuit 27
3.1.3 LC-Tank VCO Circuit 28
3.1.4 Switched-Capacitors VCO Circuit 31
3.2 Phase Frequency Detector Circuit (PFD) 33
3.3 Charge Pump Circuit (CP) 35
3.3.1 Single-Ended Charge Pump 36
3.3.2 Current-Steering Charge Pump 37
3.4 Frequency Divider 38
3.4.1 Pulse-Swallow Divider 38
3.4.2 Dual-Modulus Prescalers 39
3.4.3 Multi-Modulus Divider 40
3.4.4 Full-Modulus Divider 42
3.4.5 CML Divider and TSPC Divider 43
3.5 Σ-Δ Modulator 44
3.5.1 1st-Order Σ-Δ Modulator 44
3.5.2 Higher-Order Σ-Δ Modulator 46
3.6 Loop Filter Design 49
3.6.1 First-Order Loop Filter 50
3.6.2 Second-Order Loop Filter 52
3.6.3 Third-Order Loop Filter 55
3.7 Summary 56
Chapter 4 A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Spurious Tone Reduction Technique 57
4.1 Introduction 57
4.2 System Block Diagram 58
4.3 Building Block and Simulation 59
4.3.1 Voltage-Controlled Oscillator Circuit (VCO) 59
4.3.2 Frequency and Phase Detector Circuit (PFD) 62
4.3.3 Charge Pump Circuit (CP) 64
4.3.4 Programmable Divider Circuit 65
4.3.5 MASH 1-1-1 Σ-Δ Modulator 71
4.3.6 Sample-Hold-Reset Loop Filter 73
4.3.7 The Overall PLL System Simulation Results 75
4.4 Frequency Synthesizer Chip Measurements 77
4.4.1 Chip Floor Plan and PCB Design 77
4.4.2 Test Environment Setup 79
4.4.3 Measurement Results 80
4.5 Specifications and Performance Comparison 82
4.6 Summary 84
Chapter 5 A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Exploiting Randomly Selected PFD and Sub-Sampling Charge Pump 85
5.1 Introduction 85
5.2 System Block Diagram 87
5.3 Phase-Locked Loop Functions 87
5.3.1 Voltage-Controlled Oscillator Circuit (VCO) 88
5.3.2 Spur Reduction System 89
5.3.3 Random Clock Generator 91
5.3.4 Frequency and Phase Detector Circuit (PFD) 92
5.3.5 Sub-Sampling Charge Pump Circuit (SSCP) 92
5.3.6 Programmable Divider Circuit 94
5.3.7 The Overall PLL System Simulation Results 98
5.4 Frequency Synthesizer Chip Measurements 100
5.4.1 Chip Floor Plan and PCB Design 100
5.4.2 Test Environment Setup 101
5.4.3 Measurement Results 102
5.5 Specifications and Performance Comparison 105
5.6 Summary 107
Chapter 6 Conclusions and Future Work 109
6.1 Conclusions 109
6.1.1 Chip1: A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Spurious Tone Reduction Technique 109
6.1.2 Chip2: A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Exploiting Randomly Selected PFD and Sub-Sampling Charge Pump 109
6.2 Future Work 112
Reference 114
Appendix : Chip Tapeout List and Publication 120
[1]S.-I. Liu, “Design and Realization of CMOS RF Frequency Synthesizer,” Master Thesis, 2001.
[2]A. L. Lacaita, S. Levantino and C. Samori, “Integrated Frequency Synthesizers for Wireless Systems,” Cambridge University Pres, 2007.
[3]A. Mohammadi, A. Ayatollahi, A. Abrishamifar and A. Beygi, “Frequency Synthesizer Settling Time and Phase Noise Issues For WLAN Transceiver Application in IEEE 802.11n Standard,” Int. ICEE '07 Conf., no. 4, pp.1–5, Apr. 2007.
[4]P. J. Shie, “UWB RF Receiver Front-end Chip Design with On-Chip Transformer Circuit,” Master Thesis, 2008.
[5]H. Bellescize, “La reception synchrone,” L’onde electrique, vol. 11, no. 5, pp.225–240, May 1932.
[6]H. J. Finden, “The Frequency Synthesizer,” IEEE J. Part III, vol. 90, no. 5, pp.165-80, May. 1943.
[7]M. Kozak and I. Kale, “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis,” IEEE Trans. Instrum. Meas., vol. 50, no. 10, pp. 1154–1161, Oct. 2001.
[8]Keliu Shu Edgar Sanchez-Sinencio, “CMOS PLL Synthesizers: Analysis and Design,” New York, N.Y., Springer, 2005.
[9]A. Hajimiri and T. H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[10]W.-H. Chen, W.-F. Loke and B. Jung, “A 0.5-V, 440-μW Frequency Synthesizer for Implantable Medical Devices,” IEEE J. Solid-State Circuits, vol. 47, no. 8, pp. 1896–1907, Aug. 2012.
[11]S. Bazarjani and W. Snelgrove, “Low Voltage SC Circuit Design with Low-Vt MOSFETs,” IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, pp. 1021–1024, Apr. 1995.
[12]T. Ohguro et al., “0.18 μm Low Voltage/Low Power RF CMOS with Zero Vth Analog MOSFETs Made by Undoped Epitaxial Channel Technique,” Int. Electron Devices Meeting (IEDM), pp.837–840, Dec. 1997.
[13]A. Jimenez-P, F. de la Hidalga-W, and M. Deen, “Modelling of the Dynamic Threshold MOSFET,” IEE Circuits, Devices and Syst., vol. 152, no. 5, pp. 502–508, Oct. 2005.
[14]P. Park, D. Park and S. Cho, “A 2.4 GHz Fractional-N Frequency Synthesizer with High-OSR ΔΣ Modulator and Nested PLL,” IEEE J. Solid-State Circuits, vol. 47, no. 10, pp. 2433–2443, Oct. 2012.
[15]T. Riley, M. Copeland, and T. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993.
[16]D. Park and S. Cho, “A 14.2 mW 2.55-to-3 GHz Cascaded PLL with Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 um CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 12 , pp. 2989–2998, Dec. 2012.
[17]D. Cai, H. Fu, J. Ren, W. Li, N. Li, H. Yu, and K. S. Yeo, “A Dividerless PLL with Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter,” IEEE Trans. Circuits Syst. I, vol. 60, no. 1, pp. 37–50, Jan. 2013.
[18]X. Gao, E. Klumperink, M. Bohsali, and B. Nauta, “A Low Noise Subsampling PLL in Which Divider Noise Is Eliminated and PD/CP Noise Is Not Multiplied by N2 ,” IEEE J. Solid-State Circuits, vol. 44, pp. 3253–3263, Dec. 2009.
[19]A. Shahani et al., “Low-Power Dividerless Frequency Synthesis using Aperture Phase Detector,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2232–2239, Dec. 1998.
[20]X. Gao, E. Klumperink, G. Socci, M. Bohsali, and B. Nauta, “Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117–121, Feb. 2009.
[21]C. S. Vaucher, “Architectures for RF Frequency Synthesizers,” Norwell, MA: Kluwer, 2002.
[22]B. Razavi, “Design of Analog CMOS Integrated Circuits,” New York, NY: McGraw Hill, International Edition, 2001.
[23]H. Zhang, G. Chen and N. Li, “A 2.4-GHz Linear-Tuning CMOS LC Voltage-Controlled Oscillator,” Proceedings of the ASP-DAC, vol. 2, no. 1, pp. 799–802, Jan. 2005.
[24]A. Hajimiri and T. H. Lee, “Design Issues in CMOS Differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp.717–724, May. 1999.
[25]S. Levantino, et. al., “Frequency Dependence on Bias Current in 5-GHz CMOS VCOs: Impact on Tuning Range and Flicker Noise Up conversion,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp.1003–1011, Aug. 2002.
[26]M. Tiebout, “Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp.1018–1024, July 2001.
[27]A. Goel, and H. Hashemi, “Frequency Switching in Dual-Resonance Oscillators,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp.571–582, Mar. 2007.
[28]C.-T. Kuo, J.-Y. Chang, and S.-I. Liu, “A Spur-Reduction Technique for 5-GHz Frequency Synthesizer,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 3, pp.526–533, Mar. 2006.
[29]A. Kral, F. Behbahani, and A. A. Abidi, “RF-CMOS Oscillators with Switched Tuning,” IEEE Custom IC Conference, no. 5, pp. 555–558, May. 1998.
[30]Z. Li and K. K. O., “A 1-V Low Phase Noise Multi-Band CMOS Voltage-Controlled Oscillator with Switched Inductors and Capacitors,” IEEE RFIC Symposium, no. 6, pp.467–470, June 2004.
[31]W. Rhee, “Design of High-Performance CMOS Charge Pump in Phase-Locked Loops,” IEEE International Symposium on Circuits and Ststems, pp. 545–548, June 1999.
[32]H.-I. Lee, et. al., “A ΣΔ Fractional-N Frequency Synthesizer Using a Wide-band Integrated VCO and a Fast AFC Technique for GSM/GPRS/WCDMA Application,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp.1164–1169, July 2004.
[33]W. Rhee, B.-S. Song, and A. Ali, “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-bit Third-Order ΔΣ Modulator,” IEEE J. Solid-State Circuits, vol. 35, no. 10, pp.1453–1460, Oct. 2000.
[34]T. Morie, et. al., “A -90dBc@10kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit,” IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 52–55, June 2005.
[35]B. Razavi, “RF Microelectronics”, Prentice Hall, NY, 1998.
[36]S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, “A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-?慆 CMOS Technology,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp.1039–1045, July 2000.
[37]Y.-C. Yang, S.-A. Yu, Y.-H. Liu, T. Wang, and S.-S. Lu, “A Quantization Noise Suppression Technique for ΔΣ Fractional-N Frequency Synthesizers,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp.2500–2511, Nov. 2006.
[38]S. B. Sleiman, J. G. Atallah, S. Rodriguez, A. Rusu, and M. Ismail, “Wide-Division-Range High-Speed Fully Programmable Frequency Divider,” IEEE Workshop Circuits Syst. TAISA Conf., pp. 17-20, June 2008.
[39]C.-S. Lin, T.-H. Chien, and C.-L. Wey, “A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 9, pp. 550–554, Sep. 2011.
[40]J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp.62–70, Feb. 1989.
[41]K. Woo, Y. Liu, E. Nam and D. Ham, “Fast-Lock Hybrid PLL Combining Fractional-N and Integer Modes of Differing Bandwidths,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 379–389, Feb. 2008.
[42]T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis, ” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May. 1993.
[43]T.-H. Lin, C.-L. Ti, and Y.-H. Liu, “Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 5, pp. 877–885, May 2009.
[44]F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Trans. On Communications, vol. 28, no. 11, pp. 1849–1858, Nov. 1980.
[45]W. O. Keese, An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops, National Semiconductor Application Note, May. 1996.
[46]S.-A Yu, P. Kinget, “A 0.65-V 2.5-GHz fractional-N synthesizer with two-point 2-Mb/s GFSK data modulation,” IEEE J. solid-state circuits, vol. 44, no.9, pp. 2411–2425, Sep. 2009.
[47]C.-T. Lu, H.-H. Hsieh, L.-H. Lu, “A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 4, pp. 793–802, April 2010.
[48]B. Zhang, P. E. Allen and J. M. Huard, “A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS,” IEEE J. solid-state circuits, vol. 38, no. 6, pp. 855–865, June 2003.
[49]J.-F. Huang, W.-C. Lai, Y.-J. Lin, “Chip design of 5.1~6 GHz colpitts QVCO for WIMAX,” IEEE Inter. Conf. on Control Engineering and Communication Technology(ICCECT), pp. 715–718, Dec. 2012.
[50]J. N. Soares, Jr. and W. A. M. V. Noije, “A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC),” IEEE J. solid-state circuits, vol. 34, no. 1, pp. 97–102, Jan. 1999.
[51]S. Shekhar, D. Gangopadhyay, E.-C Woo, and D.J. Allstot, “A 2.4-GHz extended-range type-I ΣΔ fractional-N synthesizer with 1.8-MHz loop bandwith and -110-dBc/Hz phase noise,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 8, pp. 472–476, Aug. 2011.
[52]K. J. Wang, A. Swamainathan and I. Galton, “Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz Fractional-N PLL,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.2787–2797, Dec. 2008.
[53]H. Hedayati, W. Khalil and B. Bakkaloglu, “A 1 MHz Bandwidth, 6 GHz 0.18 ?慆 CMOS Type-I?n???nFractional-N Frequency Synthesizer for WiMAX Applications,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp.3244–3252, Dec. 2009.
[54]K.-H. Cheng, Y.-C. Tsai, Y.-L. Lo, “A 0.5-V 0.4-2.24 GHz inductorless phase-locked loop in a system-on-chip”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 5, pp. 849–859, May 2011.
[55]D. Z. Turker, S. P. Khatri and E. Sanchez-Sinencio, “A DCVSL delay cell for fast low power frequency synthesis applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 6, pp. 1225–1238, June 2011.
[56]T.-W. Liao, C.-M. Chen, J.-R. Su and C.-C. Hung, “Random pulsewidth matching frequency synthesizer with sub-sampling charge pump,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 12, pp. 2815–2824, Dec. 2012.
[57]T.-W. Liao, J.-R. Su and C.-C. Hung, “Spur-reduction frequency synthesizer exploiting randomly selected PFD,” IEEE Trans. Very Large Scale Integration Systems, vol. 21, no. 3, pp. 589–592, Mar. 2013.
[58]Y.-C. Huang and S.-I. Liu, “A 2.4 GHz subharmonically injection-locked PLL with self-calibrated injection timing,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp.417–428, Feb. 2013.
[59]Y.-J. E. Chen, Y.-J. Lee, and Y.-H. Yu, “Investigation of polysilicon thin-film transistor technology for RF applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 3444–3451, Dec. 2010.
[60]Y.-W. Chen, Y.-H. Yu and Y.-J. Emery Chen, “A 0.18-μm CMOS Dual-Band Frequency Synthesizer with Spur Reduction Calibration,” IEEE Microw. Wireless Compon. Lett., vol. 23, no. 10, pp. 551–553, Oct. 2013.
[61]T.-H. and W. J. Kaiser, “A 900-MHz 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop,” IEEE Journal of solid-state circuits, vol. 36, no. 3, pp. 424–431, Mar. 2001.
[62]B. Zhao, Y. Lian and H. Yang, “A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 5, pp. 1188-1199, May 2013.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔