臺灣博碩士論文加值系統

近年來，隨著無線通訊系統快速發展，各式各樣的頻率合成器被研發出來，通常傳統的鎖相迴路之迴路濾波器均使用連續時間被動式濾波器，其需要較大的電容值才能滿足系統的需求。且濾波器連接壓控振盪器的控制端點處，會有漣波效應的產生，常常需要在鎖定時間長短與參考頻率突波做取捨。
第一顆晶片，我們介紹了一個降低參考突波技巧的2.4 GHz分數型頻率合成器的架構。使用了離散時間取樣、保持、重置迴路濾波器，主要功用為隔離充電汞的輸出與VCO的控制電壓點，使PFD、CP有較好的線性度，其能達到低突波與低相位雜訊的性能，並節省使用較低迴路頻寬時，所造成的大電容面積。此頻率合成器是使用台積電所提供0.18微米CMOS製程以1伏特來完成晶片研製與量測，而量測結果顯示頻率範圍為2.21~2.52 GHz，其13.1%，頻率鎖定在2.4 GHz時，距離主頻1 MHz處的相位雜訊為-117.1 dBc/Hz，參考訊號突波高度為-65 dBc，功率消耗為15.2 mW，晶片面積含Pad後為1.06 mm2。
第二顆晶片，我們採用了次取樣充電汞與隨機選擇相位頻率偵測器來降低參考突波。此頻率合成器將電壓控制振盪器的控制端產生的漣波隨機化，這樣可使鎖相迴路輸出頻譜的參考頻率突波降低。次取樣充電汞也是用來減少控制端的漣波達到降低參考突波的效果。此頻率合成器是使用台積電所提供0.18微米CMOS製程以1伏特來完成晶片研製與量測，而量測結果顯示頻率範圍為2.235~2.579 GHz，其14.3%，頻率鎖定在2.41 GHz時，距離主頻1 MHz處的相位雜訊為-113.17 dBc/Hz，參考訊號突波高度為-70.4 dBc，功率消耗為9 mW，晶片面積含Pad後為0.695 mm2。

In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. Normally, the loop filter of a conventional PLL are using continuous-time passive loop filter, it needs a large capacitance to meet system requirements. And the control node of the VCO is directly connected to the loop filter that will introduce ripples. Usually deals with a tradeoff between the settling time and the magnitude of the reference sideband that appears at the PLL output.
The first chip, we introduce a 2.4 GHz fractional-N frequency synthesizer architecture with a reference spur reduction technique. It adopts a sample-hold-reset loop filter to isolate the charge pump output node and the VCO control node, which has a better linearity of PFD and CP. It achieves low spur and low phase noise performance, and save the capacitance area while a narrow loop bandwidth is used. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.21 GHz to 2.52 GHz corresponding to a frequency tuning range of 13.1%, a phase noise of -117.1 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -65 dBc, a power consumption of 15.2 mW and the with pads chip area is only 1.06 mm2.
The second chip, we adopt a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur. The frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. The SSCP circuit is also utilized to reduce ripples on the control voltage to achieve low spur level. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.235 GHz to 2.579 GHz corresponding to a frequency tuning range of 14.3%, a phase noise of -113.17 dBc/Hz at 1 MHz offset from 2.41 GHz, a reference spur of -70.4 dBc, a power consumption of 9 mW and the with pads chip area is only 0.695 mm2.

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Focus and Contributions 2
1.3 Organization of This Thesis 2
Chapter 2 The Basics of Frequency Synthesizers 5
2.1 Wireless Transceiver 5
2.2 Phase-Locked Loop 6
2.2.1 Integer-N Frequency Synthesizer 7
2.2.2 Fractional-N Frequency synthesizer 8
2.3 General Considerations 9
2.3.1 Phase Noise 9
2.3.2 Spurs 11
2.3.3 Jitter 12
2.4 Frequency Synthesizer Paper Survey 13
2.7 Summary 24
Chapter 3 PLL Analysis and Circuit Design 25
3.1 Voltage-Controlled Oscillator Circuit (VCO) 25
3.1.1 General Operation Principles 26
3.1.2 Ring Oscillator Circuit 27
3.1.3 LC-Tank VCO Circuit 28
3.1.4 Switched-Capacitors VCO Circuit 31
3.2 Phase Frequency Detector Circuit (PFD) 33
3.3 Charge Pump Circuit (CP) 35
3.3.1 Single-Ended Charge Pump 36
3.3.2 Current-Steering Charge Pump 37
3.4 Frequency Divider 38
3.4.1 Pulse-Swallow Divider 38
3.4.2 Dual-Modulus Prescalers 39
3.4.3 Multi-Modulus Divider 40
3.4.4 Full-Modulus Divider 42
3.4.5 CML Divider and TSPC Divider 43
3.5 Σ-Δ Modulator 44
3.5.1 1st-Order Σ-Δ Modulator 44
3.5.2 Higher-Order Σ-Δ Modulator 46
3.6 Loop Filter Design 49
3.6.1 First-Order Loop Filter 50
3.6.2 Second-Order Loop Filter 52
3.6.3 Third-Order Loop Filter 55
3.7 Summary 56
Chapter 4 A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Spurious Tone Reduction Technique 57
4.1 Introduction 57
4.2 System Block Diagram 58
4.3 Building Block and Simulation 59
4.3.1 Voltage-Controlled Oscillator Circuit (VCO) 59
4.3.2 Frequency and Phase Detector Circuit (PFD) 62
4.3.3 Charge Pump Circuit (CP) 64
4.3.4 Programmable Divider Circuit 65
4.3.5 MASH 1-1-1 Σ-Δ Modulator 71
4.3.6 Sample-Hold-Reset Loop Filter 73
4.3.7 The Overall PLL System Simulation Results 75
4.4 Frequency Synthesizer Chip Measurements 77
4.4.1 Chip Floor Plan and PCB Design 77
4.4.2 Test Environment Setup 79
4.4.3 Measurement Results 80
4.5 Specifications and Performance Comparison 82
4.6 Summary 84
Chapter 5 A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Exploiting Randomly Selected PFD and Sub-Sampling Charge Pump 85
5.1 Introduction 85
5.2 System Block Diagram 87
5.3 Phase-Locked Loop Functions 87
5.3.1 Voltage-Controlled Oscillator Circuit (VCO) 88
5.3.2 Spur Reduction System 89
5.3.3 Random Clock Generator 91
5.3.4 Frequency and Phase Detector Circuit (PFD) 92
5.3.5 Sub-Sampling Charge Pump Circuit (SSCP) 92
5.3.6 Programmable Divider Circuit 94
5.3.7 The Overall PLL System Simulation Results 98
5.4 Frequency Synthesizer Chip Measurements 100
5.4.1 Chip Floor Plan and PCB Design 100
5.4.2 Test Environment Setup 101
5.4.3 Measurement Results 102
5.5 Specifications and Performance Comparison 105
5.6 Summary 107
Chapter 6 Conclusions and Future Work 109
6.1 Conclusions 109
6.1.1 Chip1: A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Spurious Tone Reduction Technique 109
6.1.2 Chip2: A 1-V 2.4 GHz Fractional-N Frequency Synthesizer with Exploiting Randomly Selected PFD and Sub-Sampling Charge Pump 109
6.2 Future Work 112
Reference 114
Appendix : Chip Tapeout List and Publication 120

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