跳到主要內容

臺灣博碩士論文加值系統

(44.221.73.157) 您好!臺灣時間:2024/06/20 20:26
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:李婉伊
研究生(外文):Wan-Yi Lee
論文名稱:演化式影像雜訊濾波器於場域可程式化閘陣列硬體環境下的設計
論文名稱(外文):The Design of Evolvable Image Filters on Field-Programmable Gate Array
指導教授:吳志宏吳志宏引用關係
指導教授(外文):Chih-Hung Wu
學位類別:碩士
校院名稱:國立高雄大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:102
語文別:中文
論文頁數:59
中文關鍵詞:場域可程式化閘陣列影像雜訊濾波器演化式硬體直角基因程式規劃胡椒鹽雜訊脈衝突發雜訊
外文關鍵詞:field-programmable gate arrayimage filterevolvable hardware
相關次數:
  • 被引用被引用:0
  • 點閱點閱:203
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:1
演化式硬體(evolvable hardware, EHW) 是一種以演化計算(evolutionary computation)
計算為基礎,用來設計可實現在硬體上的電路設計方法,除了具有硬體執行效率上
的優勢外,也具有自適性(adaptive)的優點,在解決複雜或多變的問題上,往往有很好的
成效。近年來以EHW 為平台的影像過濾方法,大多數以軟體形式模擬之;少數以硬體
平台實現的研究僅以單一電路合成規劃進行之,對於不同類型的雜訊應用與演化參數的
效果,並未有太多的著墨。本研究以於Quartus II軟體中使用Verilog 語言撰寫可運作於
場域可程式化閘陣列(Field-Programmable Gate Array, FPGA) 平台上的EHW影像濾波
器,並於ModelSim 軟體進行模擬與驗證。研究採用模組化設計方式,將EHW 影像濾
波器的演化與測試功能,分解成獨立的電路模組,加入提升演化效率的方法,並以不同類
型的雜訊應用與演化參數進行功能測試,其結果與軟體式的EHW 影像濾波器進行分析
與比較。
Evolvable hardware (EHW) is a combination of reconfigurable hardware and evolutionary
algorithms. EHW employs evolutionary computation to attempt to find out optimal
or flexible hardware designs that can be implemented on reconfigurable hardware
platforms. With the efficiency of hardware execution and the ability of adaptibility, EHW
has advantages in solving complex problems. In most studies, the performance of EHW
algorithms, that is assumed to be implemented in a single hardware configuration, is simulated.
In this thesis, the hardware degisn of EHW-based image filters is presented. We
use Verilog in Quartus II to design EHW-based image filters to be implemented on fieldprogrammable
gate array (FPGA). The proposed design consists of seven modules and
is emulated and evaluated in ModelSim. Function-level verification of the design is performed
and studied. Various parameters associated with image noise and the evolutionary
algorithm used in EHW are tested in the experiments. The performance is analyzed and
discussed.
摘要. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ii
致謝. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
圖目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
表目錄. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
1 緒論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究背景與動機. . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究目的與方法. . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 研究流程. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 背景知識與相關文獻. . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 場域可程式化閘陣列硬體. . . . . . . . . . . . . . . . . . . . . . . 6
2.2 演化式硬體. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 直角座標式基因規劃演算法. . . . . . . . . . . . . . . . . . . . . . 8
2.4 演化式硬體的實作與應用之相關參考文獻. . . . . . . . . . . . . . . . 10
3 系統設計架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 設計構想. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 輸入緩衝模組. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 圖像濾波器模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 電路結構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 功能運算模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 亂數產生器模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 線性反饋移位暫存器. . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.2 亂數規格. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 染色體儲放模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 基因演算法運作模組. . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.1 交配機制. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.2 突變機制. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7 適應值計算模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.8 適應值比較模組. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
[1] J. Miller and P. Thomson, “Cartesian genetic programming,” in Genetic Programming (R. Poli,W. Banzhaf,W. Langdon, J.Miller, P. Nordin, and T. Fogarty, eds.), vol. 1802 of Lecture Notes in Computer Science, pp. 121–132, Springer Berlin Heidelberg, 2000.
[2] Y. Zhang, S. Smith, and A. Tyrrell, “Digital circuit design using intrinsic evolvable hardware,” in Proceedings of the NASA/DoD Conference on Evolvable Hardware, pp. 55–62, 2004.
[3] Z. Vasicek and L. Sekanina, “An area-efficient alternative to adaptive median filtering in FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 216–221, 2007.
[4] T. Martinek and L. Sekanina, “An evolvable image filter: Experimental evaluation of a complete hardware implementation in FPGA,” in Evolvable Systems: From Biology to Hardware (J. Moreno, J. Madrenas, and J. Cosp, eds.), vol. 3637 of Lecture Notes in Computer Science, pp. 76–85, Springer Berlin Heidelberg, 2005.
[5] L. Sekanina, “Image filter design with evolvable hardware,” in Applications of Evolutionary Computing (S. Cagnoni, J. Gottlieb, E. Hart, M. Middendorf, and G. Raidl, eds.), vol. 2279 of Lecture Notes in Computer Science, pp. 255–266, Springer Berlin Heidelberg, 2002.
[6] K. Vinger and J. Torresen, “Implementing evolution of fir-filters efficiently in an FPGA,” in Proceedings of the NASA/DoD Conference on Evolvable Hardware, pp. 26–29, 2003.
[7] M. Hubner, K. Paulsson, M. Stitz, and J. Becker, “Novel seamless design-flow for partial and dynamic reconfigurable systems with customized communication structures based on Xilinx Virtex–II FPGAs,” in Proceedings of the ARCS Workshops’ 05, pp. 39–44, 2005.
[8] T. Higuchi, M. Iwata, I. Kajitani, H. Yamada, B. Manderick, Y. Hirao, M. Murakawa, S. Yoshizawa, and T. Furuya, “Evolvable hardware with genetic learning,” in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 4, pp. 29–32, 1996.
[9] A. Upegui and E. Sanchez, “Evolving hardware with self-reconfigurable connectivity in Xilinx FPGAs,” in Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 153–162, 2006.
[10] T. Alho, P. Hamalainen,M. Hannikainen, and T. D. Hamalainen, “Compact modular exponentiation accelerator for modern FPGA devices,” Computers & Electrical Engineering, vol. 33, no. 5-6, pp. 383–391, 2007.
[11] K. Arakawa, “Median filter based on fuzzy rules and its application to image restoration,” Fuzzy Sets and Systems, vol. 77, no. 1, pp. 3–13, 1996.
[12] T. Arslan, “Book review: Evolvable components–from theory to hardware implementations,” Genetic Programming and Evolvable Machines, vol. 6, pp. 461–462, Dec. 2005.
[13] D. R. K. Brownrigg, “The weighted median filter,” Communications of the Association for Computing Machinery, vol. 27, pp. 807–818, Aug. 1984.
[14] T. Chen, K.-K. Ma, and L.-H. Chen, “Tri-state median filter for image denoising,” IEEE Transactions on Image Processing, vol. 8, no. 12, pp. 1834–1838, 1999.
[15] C. Lambert, T. Kalganova, and E. Stomeo, “FPGA-based systems for evolvable hardware,” in Proceedings of the International Conference on Computer Science, Mar. 2006.
[16] U. Farooq, H. Parvez, H. Mehrez, and Z. Marrakchi, “A new heterogeneous treebased application specific FPGA and its comparison with mesh-based application specific FPGA,” Microprocessors and Microsystems, vol. 36, no. 8, pp. 588–605, 2012.
[17] M. I. Ferguson, R. S. Zebulum, D. Keymeulen, and A. Stoica, “An Evolvable Hardware Platform Based on DSP and FPTA,” in Proceedings of the Genetic and Evolutionary Computation Conference, pp. 145–152, 2002.
[18] Z. Gajda and L. Sekanina, “Reducing the number of transistors in digital circuits using gate-level evolutionary design,” in Proceedings of the Genetic and Evolutionary Computation Conference, pp. 245–252, 2007.
[19] G. W. Greenwood and A. M. Tyrrell, Introduction to Evolvable Hardware : A Practical Guide for Designing Self-adaptive Systems. A John Wiley & Son, Inc., Oct. 2007.
[20] J. Hilder, J. Walker, and A. Tyrrell, “Use of a multi-objective fitness function to improve cartesian genetic programming circuits,” in Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 179–185, 2010.
[21] G. Hollingworth, S. Smith, and A. Tyrrell, “The intrinsic evolution of virtex devices through internet reconfigurable logic,” in Evolvable Systems: From Biology to Hardware (J.Miller, A. Thompson, P. Thomson, and T. Fogarty, eds.), vol. 1801 of Lecture Notes in Computer Science, pp. 72–79, Springer Berlin Heidelberg, 2000.
[22] T. Huang, G. Yang, and G. Tang, “A fast two-dimensional median filtering algorithm,” IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 27, no. 1, pp. 13–18, 1979.
[23] S.-J. Ko and Y.-H. Lee, “Center weighted median filters and their applications to image enhancement,” IEEE Transactions on Circuits and Systems, vol. 38, no. 9, pp. 984–993, 1991.
[24] P. Koivisto, J. Astola, V. Lukin, V. Melnik, and O. Tsymbal, “Removing impulse bursts from images by training-based filtering,” EURASIP Journal on Advances in Signal Processing, vol. 2003, no. 3, pp. 472–580, 2003.
[25] P. T. Koivisto, H. Huttunen, and P. Kuosmanen, “Training-based optimization of soft morphological filters.,” Journal Electronic Imaging, vol. 5, no. 3, pp. 300–322, 1996.
[26] D. A. M. K. J.R. Koza, F.H. Bennett III and F. Dunlap, “Automated synthesis of analog electrical circuits by means of genetic programming,” IEEE Transactions on Evolutionary Computation, vol. 1, no. 2, pp. 109–128, 1997.
[27] R. Kumar and S. K. Srivathsa, “EHW Architecture for Design of Adaptive Median Filter for Noise Reduction,” European Journal of Scientific Research, vol. 36, pp. 473–479, 2009.
[28] K. Latif, A. Aziz, and A. Mahboob, “Optimal utilization of available reconfigurable hardware resources,” Computers & Electrical Engineering, vol. 37, no. 6, pp. 1043–1057, 2011.
[29] D. J. J. F.Miller and V. K. Vassilev, “Principles in the evolutionary design of digital circuits - part i,” Genetic Programming and Evolvable Machines, vol. 1, no. 1-2, pp. 7–35, 2000.
[30] J. Miller and S. Smith, “Redundancy and computational efficiency in cartesian genetic programming,” IEEE Transactions on Evolutionary Computation, vol. 10, no. 2, pp. 167–174, 2006.
[31] S.-T. Pan and X.-Y. Li, “An FPGA-based embedded robust speech recognition system designed by combining empirical mode decomposition and a genetic algorithm,” IEEE Transactions on Instrumentation and Measurement, vol. 61, no. 9, pp. 2560–2572, 2012.
[32] S. Schulze and S. Sawitzki, “Processor design using a functional hardware description language,” Microprocessors and Microsystems, vol. 36, no. 8, pp. 676–694, 2012.
[33] L. Sekanina, “Evolutionary design of digital circuits: Where are current limits?,” in Proceedings of the 1st NASA/ESA Conference on Adaptive Hardware and Systems, pp. 171–178, 2006.
[34] L. Sekanina, “Virtual reconfigurable circuits for real-world applications of evolvable hardware,” in Proceedings of the 5th international conference on Evolvable systems: from biology to hardware, ICES’03, (Berlin, Heidelberg), pp. 186–197, Springer-Verlag, 2003.
[35] M. Sipper, “Designing evolware by cellular programming,” in Evolvable Systems: From Biology to Hardware (T. Higuchi, M. Iwata, and W. Liu, eds.), vol. 1259 of Lecture Notes in Computer Science, pp. 79–95, Springer Berlin Heidelberg, 1997.
[36] T. Sun and Y. Neuvo, “Detail-preserving median based filters in image processing,” Pattern Recognition Letters, vol. 15, no. 4, pp. 341–347, 1994.
[37] Z. Vasicek, M. Bidlo, L. Sekanina, J. Torresen, K. Glette, and M. Furuholmen, “Evolution of impulse bursts noise filters,” in Proceedings of the NASA/ESA Conference on the Adaptive Hardware and Systems, pp. 27–34, 2009.
[38] Z. Vasicek and L. Sekanina, “Reducing the area on a chip using a bank of evolved filters,” in Evolvable Systems: From Biology to Hardware (L. Kang, Y. Liu, and S. Zeng, eds.), vol. 4684 of Lecture Notes in Computer Science, pp. 222–232, Springer Berlin Heidelberg, 2007.
[39] Z. Vasicek and L. Sekanina, “A global postsynthesis optimizationmethod for combinational circuits,” in Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–4, 2011.
[40] Z. Vasicek and L. Sekanina, “Novel hardware implementation of adaptive median filters,” in Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 1–6, 2008.
[41] Z. Vasicek and L. Sekanina, “Evaluation of a new platform for image filter evolution,” in Proceedings of the 2nd NASA/ESA Conference on Adaptive Hardware and Systems, pp. 577–586, 2007.
[42] Z. Vasicek and L. Sekanina, “An evolvable hardware system in Xilinx Virtex II Pro FPGA,” International Journal of Innovative Computing and Applications, vol. 1, 2007.
[43] Z. Vasicek, L. Sekanina, and M. Bidlo, “A method for design of impulse bursts noise filters optimized for FPGA implementations,” in Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1731–1736, 2010.
[44] V. Vassilev, D. Job, and J. Miller, “Towards the automatic design of more efficient digital circuits,” in Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 151–160, 2000.
[45] X. Yao and T. Higuchi, “Promises and challenges of evolvable hardware,” IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews, vol. 29, no. 1, pp. 87–97, 1999.
[46] Y. Zhang, S. Smith, and A. Tyrrell, “Intrinsic evolvable hardware in digital filter design,” in Applications of Evolutionary Computing, vol. 3005 of Lecture Notes in Computer Science, pp. 389–398, Springer Berlin Heidelberg, 2004.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top