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研究生(外文):Hema E P
論文名稱(外文):Low Cost UMOS Design, Hspice Macro Model to Fit the ESD Behavior of 5V NMOS, and Integration of LIGBT with 0.35um BCD Technology
指導教授:許健許健引用關係
指導教授(外文):Gene Sheu
口試委員:楊紹明許健簡鳳佐
口試委員(外文):Shao-Ming YangGene SheuFeng-Tso Chien
口試日期:2014-05-26
學位類別:碩士
校院名稱:亞洲大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:53
外文關鍵詞:UMOSESDIGBTForward Voltageturn-off timeShorted anodeggNMOS
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ABSTRACT ii
ACKNOWLEDGEMENT iii
TABLE OF CONTENETS iv-v
List of Figures vi-vii
List of Tables viii
CHAPTER 1 1-8
INTRODUCTION 1-2
1.1 History of Power Devices 2-3
1.2 Applications of Power Devices 4-6
1.3 Power device Reliability 6-7
1.4 Thesis motivation and objective 7
1.5 Overview 8
CHAPTER 2 9-18
VERTICAL POWER MOSFET(UMOS) 9
2.1 Evolution of Low Voltage Vertical Power MOSFET 9-11
2.2 Advantages of UMOS over DMOS 11
2.2.1 Leakage current 11-12
2.2.2 Breakdown voltage 12-13
2.2.3 On-Resistance 13-14
2.3 UMOS DESIGN AND SIMULATION 14-18
2.3.1 DependanceofEpitaxialthickness 14-15
2.3.2 Interstitial effect on UMOS performance 15-18
2.4 Conclusion 18
CHAPTER 3 19-27
HSPICE Macro model for the ESD Behavior of Gate Grounded NMOS and Gate bias NMOS 19
3.1 What is ESD? 19
3.2 On-chip ESD protection 19-21
3.3 ESD protection devices: Physics and operation 21-22
3.4 Hspice simulation and Result discussion 23-27
3.5 Conclusion 27
CHAPTER 4 29-49
An integrable JI-LIGBT with UHV 800V and 0.35um BCD Technology 29
4.1 Introduction 29
4.2 Advantages of IGBT over a Power MOSFET and a BJT 29-30
4.2.1 Advantages 29
4.2.2 Drawbacks 30
4.3 IGBT basics 30-32
4.4 Operation modes of IGBT 32
4.4.1 Forward-blocking and conduction modes 31-32
4.4.2 Reverse-blockingmode 32
4.4.3 Outputcharacteristics 33
4.4.4 Transfer characteristics 33-35
4.4.5 Switching characteristics 35-36
4.4.6 Latch-up 36-37
4.5 Techniques used in Lateral Insulated Gate Bipolar Transistor 38-41
4.5.1Junction Isolated LIGBT 38-41
4.5.1.1 Conventional LIGBT with buried layer, sinker and hole diverter 38-39
4.5.1.2 Shorted-anode LIGBT(SA-LIGBT) 39
4.5.1.3 Improved SA-LIGBT Techniques 39-40
4.5.1.4 Lateral Trench-Gate Bipolar Transistor(LTGBT) 41
4.6 Proposed Device Structure 40-44
4.7 Device simulation 44-49
4.8 Conclusion 49
CHAPTER 5 50
CONCLUSION 50

LIST OF FIGURES

Fig 1.1 Classification of power semiconductor 3
Fig1.2 Power ranges of commercially available power semiconductors 4
Fig1.3 Applications and power ranges of power devices 5
Fig1.4 Trade-off characteristics of LDMOS (a) SOA, breakdown and on-resistance (b) Effects on device ruggedness 6
Fig2.1 structure of a typical VMOS 9
Fig2.2 (a) VDMOS and (b) UMOS 10
Fig2.3 Cross section of DMOS and UMOS 11
Fig2.4 Temperature effect on Leakage current 12
Fig2.5 Temperature effect on Breakdown voltage 13
Fig2.6 Temperature effect on On-resistance 14
Fig2.7 Cross section of UMOS 15
Fig2.8(a)Interstitials distribution for Taurus implant, pair and React diffusion model 16
Fig2.8(b)Interstitials distribution for Monte Carlo implant, pair and React diffusion model 16
Fig2.9 Vacancy distribution for Taurus/Monte Carlo implant and pair/React diffusion model 17
Fig2.9.1 Shows vertical phosphorus profile at x=0.1um and x=0.75um(near polygate) 17
Fig3.1The generic configuration of the ESD protection circuit in a bi-directional I/O circuit 21
Fig3.2 Schematic I-V curve of a typical NMOS transistor for different gate bias 23
Fig3.3 Proposed Macro model circuit 24
Fig3.4 Comparison of fitting result and Si result for Vh and Vt1 26
Fig3.5 Fitting parameters : Rs and Tref for different gate bias 27
Fig4.1 Schematic view of a generic N-channel IGBT 29
Fig4.2 (a) Equivalent circuit model of an IGBT (b) IGBT circuit symbol 30
Fig4.3 Structure (a) NPT-IGBT and (b) PT-IGBT 30
Fig4.4 Output I-V characteristics of an NPT-IGBT 33
Fig4.5 IGBT Transfer characteristics 34
Fig4.6 Trans-conductance characteristics of an IGBT 34
Fig4.7 IGBT Switching time test circuit 35
Fig4.8 IGBT current and voltage turn-on and turn-off waveforms 36
Fig4.9 On-state current flow path of an IGBT 37
Fig4.6.1 (a) Schematic cross-sectional view JI-LIGBT using multiple RESURF technology with linearly degraded P-top engineering 41
Fig4.6.1 (b) Embodiment to the proposed structure 41
Fig4.6..2 Mask design of linearly degraded P-top structure 42
Fig4.6.3 MATLAB masking tool for determining the locations and widths of linearly degraded P-top 43
Fig4.7.1 (a) Process simulated JI-LIGBT embodiment-1 45
Fig4.7.1 (b) Process simulated JI-LIGBT embodiment-2 45
Fig4.7.2 Anode side N+ and P layer masking 46
Fig4.7.3 Anode side Net Doping Profile 46
Fig4.7.4 Electric Field profile 47
Fig4.7.5 Forward Voltage drop 47
Fig4.7.6 Shows the turn off curve 48

LIST OF TABLES

Table2.1 Temperature versus Leakage current 12
Table2.2 Temperature versus Breakdown voltage 12
Table2.3 Temperature versus On-resistance 13
Table2.4 Simulation Result 14
Table2.5 Epi thickness versus electrical characteristics 15
Table2.6 Device characteristics 18
Table3.1 Fitting parameters 27
Table4.1 Characteristics comparison of NPT and PT IGBTs 31
Table4.2 Categories of LIGBT 38
Table4.3 Process flow 44










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