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研究生:柯興男
研究生(外文):Hsin-Nan Ke
論文名稱:利用步階阻抗架構降低差動傳輸線轉角之共模雜訊
論文名稱(外文):Applying The Stepped-Impedance Structure to Reduce The Common-Mode Noise for Bended Differential Transmission Lines
指導教授:林丁丙林丁丙引用關係
口試委員:黃建彰馬自莊林信標吳宗霖
口試日期:2014-06-18
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:55
中文關鍵詞:步階阻抗傳輸線慢波特性共模雜訊時序偏差訊號完整性
外文關鍵詞:stepped impedance transmission lineslow-wavecommon-mode noisetiming skewsignal integrity
相關次數:
  • 被引用被引用:2
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  • 下載下載:78
  • 收藏至我的研究室書目清單書目收藏:0
本論文主要目的為設計步階阻抗傳輸線結構於轉角差動微帶線,實現於印刷電路基板上,具有價格低廉且電路體積小之優點。利用步階阻抗傳輸線結構的慢波特性以補償內側走線與外側走線的訊號傳播速度來降低差動訊號走線因轉角造成時序偏差而產生的共模雜訊。在頻域分析上,其差模共模轉換損耗從DC到高頻8GHz皆能維持在-20dB之下。在時域分析上,能有效降低共模雜訊電壓從0.067V降至0.006V達91%以上。並且我們也建立出有步階阻抗傳輸線結構的差動傳輸線等效電路模型以及萃取其電感-電容矩陣值。因此,將其值代入計算工具設計出步階阻抗傳輸線在差動線對的最佳結構。最後根據模擬與實驗結果可進一步證明本文所提出步階阻抗結構能有效降低其共模雜訊的成分,同時還能維持良好的差模訊號完整性。

The main purpose for this paper is the design of the stepped impedance transmission line (SITL) structure in bended differential transmission lines. The advantages of the design are with lower price and smaller circuit area when realizing it in print circuit board (PCB). To take advantage of the characteristic of SITL structure and slow-wave property to compensate for the signal propagation velocity of inner trace and outer trace can reduce common-mode noise generated from timing skew caused by the bended differential signal line. In the frequency domain analysis, the differential-mode to common-mode conversion (Scd21) from DC to high frequency 8GHz is greatly under -20dB. In the time domain analysis, it effectively reduces common-mode noise voltage more than 91%, from 0.067V down to 0.006V. We also established the equivalent circuit model of the differential transmission lines in SITL structure, and extracted its L-C matrix values. Then, the values are imported into calculation tools to design the optimum structure out of the SITL structure in differential transmission line pair. Finally, the simulation and experimental results can prove that the proposed SITL structure in this paper can effectively reduce the common-mode noise, while maintaining good differential-mode signal integrity.

第一章 緒論 1
1.1 研究背景與動機 1
1.2 文獻探討 4
1.3 論文架構 8
第二章 差動傳輸系統與步階阻抗傳輸線基礎理論 9
2.1 差動(Differential)訊號傳輸技術 9
2.2 耦合傳輸線(coupled transmission line) 11
2.3 奇模(Odd-mode)與偶模(Even-mode)傳輸分析 12
2.3.1 耦合微帶傳輸線原理 12
2.3.2 奇模傳輸之特性分析 14
2.3.3 偶模傳輸之特性分析 16
2.4 差動電路特性分析與量測 18
2.4.1 混合模態散射參數(mixed-mode S-parameter) 19
2.5 步階阻抗傳輸線原理簡介 23
第三章 步階阻抗傳輸線實現於差動傳輸線轉角處之分析與設計 25
3.1 差動傳輸線轉角處分析 25
3.2 步階阻抗傳輸線結構導入差動線對之設計 29
3.2.1週期性波慢特性之步階阻抗傳輸線設計 29
3.2.2 步階阻抗傳輸線等效電路與時序落差分析 32
3.3 本架構最小時序落差值之步階阻抗傳輸線設計 36
第四章 模擬與實測結果討論 40
4.1 步階阻抗傳輸線實現於轉角結構之頻域分析討論 41
4.2步階阻抗傳輸線實現於轉角結構之時域分析討論 47
第五章 結論 52
參考文獻 53


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