臺灣博碩士論文加值系統

非同步電路已經逐漸受到重視，然而非同步電路相關的發展較同步電路慢，且設計工具也並不完備。首先是電路合成工具的問題，現有之合成工具並不支援非同步電路之合成。因此本論文之電路設計是採用大同大學資工系所開發之合成工具。其次是標準元件庫的問題，雖然我們可以使用一般同步電路之標準元件庫，但所得到的電路通常性能不好，且具有安全性問題，因此我們必須準備非同步電路的標準元件庫。本篇論文使用台積電 0.18μm CMOS 1P6M之製程設計標準元件庫，並實現非同步電路的基本元件C-element與多個輸入之動態NOR閘，並在Cell-based design flow驗證此標準元件庫。
模擬結果顯示，使用電晶體層級的C-element比沒有使用的面積下降了23%。另外，以ISCAS85電路來比較三種準延遲漠然電路NCL_D、NCL_X及ROC在組合電路的表現，結果顯示NCL_X比NCL_D平均面積小40%，ROC比NCL_D少46%。比較三種準延遲漠然電路在循序電路的表現，結果顯示NCL_X比NCL_D平均面積小24%，ROC比NCL_D少28%。

More and more research focuses on asynchronous circuit. However, development of asynchronous circuits lag behind synchronous circuits and EDA tools are not mature. Moreover, most of synthesis tools do not support synthesis of asynchronous circuits. Therefore, we employ an asynchronous circuit synthesis tool developed by the research team from Department of Computer Science and Information Engineering in Tatung University. The other problem is standard cell library. Using normal standard cell library causes poor performance, and hazards. Therefore, asynchronous cell library is necessary. In this thesis, asynchronous cell library is designed and implemented under TSMC 0.18μm CMOS 1P6M process. The C-element, a basic cell for asynchronous circuits, and multi-input dynamic NOR are designed and validated with cell-based design flow.
From the simulation results, average cell area of NCL_D QFSM is reduced by 23% with the use of transistor-level implementation of C-element. Using our cell library to implement ISCAS85 circuits with NCL_D, NCL_X, and ROC QDI circuits in Design Compiler, the average area of ROC is reduced by 46%, and average area of NCL_X is reduced by 40% compared to NCL_D. For the QDI FSM implementation, the average area of ROC QFSM is reduced by 28%, and the average area of NCL_X QFSM is reduced by 24% compared to NCL_D.

ACKNOWLEDGEMENT i
ENGLISG ABSTRACT ii
CHINESE ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 1
CHAPTER 2 BACKGROUND REVIEW 2
2.1 Asynchronous Digital System 2
2.1.1 Asynchronous Combination Circuits 4
2.1.2 Asynchronous Sequential Circuits 7
2.2 Cell-base Design 10
2.2.1 Technology Library 11
2.2.2Power Dissipation in circuits 13
2.2.3 Classification of Time 14
2.2.4 Nonlinear delay model 15
2.2.5 Basic layout rule 16
2.2.6 Library Exchange Format 17
2.2.7 Verilog library 19
CHAPTER 3 DESIGN OF CELL LIBRARY 21
3.1 Design flow of cell library 21
3.2 Core Cell layout rule 22
3.3 Creating LEF with Abstract Generator 23
3.4 Cell Characterization with Altos Liberate 24
3.5 Implementation of Asynchronous standard cells 27
CHAPTER 4 IMPLEMENTATION OF ASYNCHRONOUS DESIGN 31
4.1 Library Verification With Cell-based Design Flow 31
4.2 Simulation results 37
CHAPTER 5 CONCLUSION 39
REFERENCES 40

[1]J. Sparso, Asynchronous circuit design - A tutorial, 2001.
[2]J. Sparso, J. Staunstrup, and M. Dantzer-S renson. “Design of delay insensitive circuits using multi-ring structures,” in Proc. EuroDAC’92, pp. 15–20, Sep. 1992.
[3]A. Kondratyev, K. Lwin, “Design of Asynchronous Circuits Using Synchronous CAD Tools,” IEEE Design and Test of Computers, vol. 19, no. 4, pp. 107–117, Jul. 2002.
[4]F.-C. Cheng and C. Chen, “Can QDI combinational Circuits be implemented without C-elements?,” in Proc. ASYNC’13, pp. 134–141, May 2013.
[5]K. M. Fant and S.A. Brandt, “NULL Convention Logic™: a complete and consistent logic for asynchronous digital circuit synthesis,” in Proc. ASAP 96, pp. 261–273, Aug. 1996.
[6]F.-C. Cheng, Y.-F. Chen, S.-C. Huang, and C.-Y. Huang, “Synthesis of QDI FSMs from Synchronous Specifications,” in Proc. ASYNC’14, pp. 61–68, May 2014.
[7]Library Compiler™ Methodology and Modeling Functionality in Technology Libraries User Guide, Version E-2010.12, Mar. 2011.
[8]Library Compiler™ Timing, Signal Integrity, and Power Modeling User Guide, Version H-2013.03, Mar. 2013.
[9]CadenceR Abstract Generator User Guide, Product Version 5.1.41 July 2007.
[10]IEEE Standard for VerilogR Hardware Description Language, IEEE Std, 2005.
[11]Liberate™ Library View Creator User Guide, Version 3.0-p1 July 2010.
[12]M. Shams, J. C. Ebergen, M. I. Elmasry, “A Comparison of CMOS Implementations of an Asynchronous Circuits Primitive: the C-Element,” in Proc. Of the Intl Symposium on Low Power Electronics and Design, pp. 93–96, Aug. 1996.
[13]K. V. Berkei, “Beware the isochronic fork,” Integration, The VLSI J., vol. 13, pp. 103–128, June 1992.
[14]S. Yancey, and S. C. Smith, “A differential design for C-elements and NCL gates,” in Proc. 53rd IEEE MWSCAS, pp. 288–291, Aug. 2010.
[15]M. Moreira, B. F. Oliveira, N. Calazans, “Impact of C-elements in asynchronous circuits,” in Proc. ISQED, pp. 437–343, Mar. 2012.