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研究生:張凱智
研究生(外文):Kai-Chih Chang
論文名稱:針對輕重負載電容所設計之兩種電壓緩衝低壓降穩壓器
論文名稱(外文):TWO VOLTAGE-BUFFERED LDO REGULATORS FOR LIGHT AND HEAVY CAPACITIVE LOADS
指導教授:黃淑絹黃淑絹引用關係
指導教授(外文):Shu-Chuan Huang
口試委員:黃淑絹
口試委員(外文):Shu-Chuan Huang
口試日期:2014-07-22
學位類別:碩士
校院名稱:大同大學
系所名稱:電機工程學系(所)
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:75
中文關鍵詞:能隙參考電壓電路低壓降線性穩壓器電壓緩衝器
外文關鍵詞:bandgap reference circuitLow dropout regulatorvoltage buffer
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在可携式電子產品的發展中高能量效率的電源管理系統越來越顯得重要。電源管理系統需要有好的穩壓效能和快速的負載暫態響應才能讓可携式電子產品充分的利用有限電池能量維持系統運作。
電源管理系統上常常需要提供很多不同的電壓位準給很多模組,電源轉換器有兩種,一種是切換式穩壓器,另一種就是線性穩壓器。而近年來低壓降線性穩壓器(LDO)在其低功耗、低成本、體積小、穩定性及精確度高…等特性成為目前最常使用且較具競爭力的穩壓器,其目前廣泛的應用在電子產品,如手機、筆電、儀器…等,成為降壓穩壓電路的主流。
本論文將提出兩種補償方式,能夠將低壓降線性穩壓器有快速且穩定的負載暫態響應。本篇論文使用TSMC 0.35um2P4M的製程,設計兩種有電壓緩衝器的電路,驗證結果說明分別為(一)輸入電壓2.5V~4.5V,輸出電壓為2.3V,負載電容1?媹,(二)輸入電壓1.2V~4.5V,輸出電壓為1V,負載電容100pF;兩種電路的最大負載電流皆定為100mA,而電壓調整率及負載調整率及性能指標皆均滿足設計要求。而整個晶片面積約1058um × 947um。
Higher energy efficiency power management systems become more and more important for portable devices. Power management systems need to have better regulating performance and fast load transient response to provide the stable operation of the portable devices with limited battery energy.
Power management system need provide different voltages for all kinds of modules. There are two different types for voltage regulators: one is switching converter and the other one is linear regulator. In recent years, low-dropout linear regulator (LDO) has the features of low power consumption, smaller, stability, accuracy and low cost. It is used in many applications such as mobile phones, laptops, equipment, etc. It becomes the voltage regulator in main market.
Two compensation methods for low dropout voltage regulators with fast and stable load transient response are presented in this thesis. Using TSMC 0.35um 2P4M process, two LDO regulators with voltage buffer have been designed. One can operate in 1?媹 load capacitance with input voltage range of 2.5V-4.5V and output voltage of 2.3V. The other can operate in 100pF load capacitance with input voltage range of 1.2V-4.5V and output voltage of 1V. The maximum load current for both circuits are 100 mA, and the performance parameters meet the design requirement. The entire chip area is about 1058um × 947um .
致謝 I
摘要 II
ABSTRACT III
目次 IV
圖次 VII
表次 XI
第一章 緒論 1
1.1 研究背景 1
1.1.1 切換式穩壓器 1
1.1.2 線性穩壓器 1
1.2 研究動機 2
1.3 研究發展及流程 3
1.4 論文組織架構 3
第二章 低壓降穩壓器之重要特性參數之介紹 4
2.1 低壓降穩壓器基本原理 4
2.2 低壓降線性穩壓器之規格與定義 6
2.2.1 輸出電壓差(Dropout Voltage) 6
2.2.2 線性調整率(Line Regulation) 7
2.2.3 負載調整率(Load Regulation) 9
2.2.4 接地電流(Quiescent Current) 10
2.2.5 電源效率(Power Efficiency) 11
2.2.6 電流效率(Current Efficiency) 11
2.2.7 暫態響應(Transient Response) 12
2.2.8 頻率響應(Frequency Response) 14
2.2.9 等效串聯電阻(ESR : Equivalent Series Resistance) 17
2.2.10 電源拒斥比(Power Supply Rejection Ratio) 19
2.2.11 電壓精確度(Accuracy) 19
2.2.12 穩定度(Stability) 21
2.2.13 誤差放大器 22
2.2.14 導通元件的選用(Pass Element) 22
2.3 頻率補償的方式 24
2.3.1 米勒補償 24
2.3.2 緩衝器補償 24
第三章 能隙參考電壓電路之特性介紹與設計實現 25
3.1 簡介 25
3.2 能隙參考電壓電路原理 25
3.2.1 負溫度係數電壓 26
3.2.2 正溫度係數電壓 26
3.2.3 傳統的能隙參考電壓電路 27
3.3 文獻回顧 30
3.4 電路實現 31
3.5 電路模擬結果 32
3.5.1 輸入-輸出特性曲線 32
3.5.2 參考電壓與溫度的關係 33
3.5.3 電源拒斥比 36
第四章 低壓降線性穩壓器的設計與實現 37
4.1 研究動機 37
4.2 誤差放大器的設計 37
4.3 電壓緩衝器 38
4.4 文獻回顧 39
4.4.1 HLVB 42
4.4.2 LLVB 43
4.5 電路實現 44
4.5.1 HLVB 44
4.5.2 LLVB 45
4.6 電路之模擬結果 46
4.6.1 HLVB LDO模擬結果 47
4.6.2 LLVB 模擬結果 57
4.7 LLVB 的IC佈局 68
第五章 結論 70
5.1 結論 70
5.2 未來展望 70
參考文獻 72
[1]M. X. Zhao, Super current minor in low-dropout regulator for achieving fast transient response, Department of Electrical and Control Engineering, National Chiao Tung Univ. , MS Thesis, Jul. 2008.
[2]G. A. Rincon-Mora, “Current efficient low voltage low drop-out regulators, ” Georgia Institute of Technology, Ph. D. Thesis,Nov. 1996.
[3]Y. S. Shyu, Low operating current analog integrated circuits, National Chiao Tung Univ. , Taiwan, PhD Thesis, Jun. 2002.
[4]梁適安編著,交換式電源供應器之理論與實務設計,全華書局 民國90年。
[5]S. T. Lee, Design and implementation of low power-bound current-to-conversion dropout linear regulator integrated circuits, Department of Electrical and Control Engineering and Communication Engineering, National Taipei Univ. of Technology, MS Thesis, Jun. 2007.
[6]B. Wolbert, “Design with low dropout voltage regulators, ” Application Note, Micrel Semiconductor, Dec. 1998.
[7]C. Y. Huang, An improved frequency compensation technique for low dropout regulator, Institute of Electronics Engineering, National Tsing Hua Univ. , MS Thesis, Jun. 2004.
[8]“Technical review of low dropout voltage regulator operation and performance, ” Application Report, Texas Instruments, Aug. 1999.
[9]Z. H. Huang , Design and implementation of filters and oscillators based on current-mode active elements, Department of Electrical and Control Engineering and Communication Engineering, National Taipei Univ. , MS Thesis, Jun. 2007.
[10]B. M. King, “Advantages of using PMOS-type low-dropout linear regulators in battery applications, ” Analog Application Journal, Aug. 2000.
[11]Y. T. Ma, Fast transient response LDO for low power and low voltage system, Department of Electrical Engineering, National Chung Cheng Univ., MS Thesis, Oct. 2009.
[12]B. M. King, “Understanding the load-transient response of LDOs, ”Texas Instruments Analog Application Journal, pp. 19-21, Nov 2000.
[13]R. J. Milliken, “A capacitor-less low drop-out voltage regulator with fast transient response, ” Texas A&M Univ. , M.S. Thesis, 2005.
[14]C. M. Chen, A new frequency compensated low-dropout voltage regulator with wide stable range and high precision, Electrical and Computer Engineering, National Chiao-Tung Univ. , MS Thesis, Jan. 2007.
[15]C. M. Pan, Low power-bounce current-mode low dropout voltage regulator, Department of Electrical and Control Engineering and Communication Engineering, National Taipei Univ. of Technology, MS Thesis, Jun. 2007.
[16]V. Gupta, G. A. Rincon-Mora and P. Raha, “Analysis and design of monolithic, high PSR, linear regulators for SoC applications, ” in Proc. IEEE SoC Conf, Santa Clara, Califomia, pp. 311-315, 2004.
[17]Y. M. Chen, Design and implementation of new on-chip current-mode dc-dc buck converter and low-dropout voltage regulator with negative input-output voltage, Department of Electrical and Control Engineering and Communication Engineering, National Taipei Univ. of Technology, MS Thesis,Jun. 2007.
[18]K. N. Leung, and P. K. T. Mok, “A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation, ”IEEE J. Solid-Slate Circuits, vol. 38, no. 10, pp. 1691-1701, Oct. 2003.
[19]B. B. Lai, Design and implementation of low-dropout voltage regulator with dual-loop controlled paths and average-current-controlled buck converter, Department of Electrical and Control Engineering and Communication Engineering, National Taipei Univ. of Technology, MS Thesis, Jun. 2009.
[20]R. Stair, J. A. Connely, and M. Pulkin, “A current-mode CMOS voltage reference,” 2000 Southwest Symposium on Mixed-Signal Design, pp. 23-26, 2000.
[21]B. Song and P. R. Gray, “A precision curvature-compensated CMOS bandgap reference, ” IEEE J. Solid-Slate Circuits,vol.18, pp. 634-643, Dec. 1983.
[22]Z. Y. Zeng, A low dropout voltage regulator with high power supply rejection, Department of Electrical Engineering, National Cheng Kung Univ., MS Thesis, Jul. 2008.
[23]C. K. Wang, Research and design of low voltage high PSRR bandgap circuit, Department of Electrical Engineering, National Chiao Tung University, MS Thesis, Aug. 2006.
[24]Malcovati, P. ; Maloberti, F. ; Pruzzi, M. and Fiocchi, C. , “Curvature compensated BiCMOS bandgap with 1V supply voltage, ”in Proc. ESSCIRC, pp. 7~21 Sept. 2000.
[25]Banba, H. ; Shiga, H. ; Umezawa, A. ; Miyaba, T. ; Tanzawa, T. ; Atsumi, S. and Sakui, K. , “A CMOS bandgap reference circuit with sub-1-V operation, ” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May 1999.
[26]K. E. Kuijk, “A precision reference voltage source, ” IEEE J. Solid-Slate Circuits, vol. 8, pp. 222-226, Jun. 1973.
[27]G. Giustolisi, G. Palumbo, E. Spitale, “Robust miller compensation with current amplifiers applied to LDO voltage regulators,” IEEE Trans. on Circuits and Syst. I: Regular Papers , vol.59, no.9, pp. 1880-1893, Sept. 2012.
[28]K. N. Leung, Y. S. Ng, “A CMOS low-dropout regulator with a momentarily current-boosting voltage buffer, ” IEEE Trans. Circuits and Syst. I: Regular Papers , vol.57, no.9, pp.2312-2319 , Sept. 2010.
[29]R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator, ” IEEE Trans. Circuits Syst. I, vol. 54, no. 9, pp. 1879–1890, Sept. 2007.
[30]S. K. Lau, P. K. T. Mok, and K. N. Leung, “A low-dropout regulator for SoC with Q-reduction, ” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 658–664, Mar. 2007.
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