|
[1]B. Parhami, Computer arithmetic: algorithms and hardware Design, 2nd Edition,
Oxford University Press, New York, 2010.
[2]K. Andra, C. Chakrabarti, T. Acharya, ” A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform,. ” IEEE Trans. Signal Processing, Vol. 50, pp. 966-977, April 2000.
[3]R. Zimmermann, “Efficient VLSI Implementation of modulo (2n狰1) addition and multiplication,” in Proc. 14th IEEE Symp. Computer Arithmetic, Adelaide, Australia, Apr. 1999.
[4]K.A. Gbolagade and S.D. Cotofana. Residue number system operands to decimal conversion for 3-moduli sets. Proceedings of 51st IEEE Midwest Symposium on Circuits and Systems,pp.791-794, Knoxville, USA, August, 2008.
[5]A.A. Hiasat and H.S. Abdel-AtyZohdy. Residue -to-binary arithmetic converter for the moduli set {2k, 2k −1, 2k−1−1}. IEEE Transactions on Circuits and Systems-II Analog and Digital Signal Processing, Vol.45, No. 2, pp. 204-209, Feb.,1998.
[6]A.S. Molahosseini and K. Navi. New arithmetic residue to binary converters. International Journal of Computer Sciences and Engineering Systems, Vol. 1, No.4, pp. 295-299, October, 2007.
[7]P.V.A. Mohan. Rns-to-binary converter for a new three-moduli set {2n+1-1, 2n, 2n-1}. IEEE Trans. on Circuits and Systems-II: Express briefs, Vol. 54, No.9, pp. 775-779, September, 2007.
[8]M. Sheu S. Lin and C. Wang. Efficient vlsi design of residue to binary converter for the moduli set {2n,2n+1−1,2n−1}. IEICE Trans. INF. and SYST., Vol. E91-D, No.7, pp. 2058-2060, July,2008.
[9]A.S. Molahosseini et al., “A new residue to binary converter based on MRC,” 3rd Int. Conf. on ICTTA, pp. 1-6, 2008.
[10]K.A. Gbolagade et al., “An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set,” Proceedings of IEEE Int. Symp. on ISCAS, pp. 2103- 2106, 2010.
[11]A. S. Molahosseini et al., “A new design of reverse converter for a three-moduli set,” Inte. Symp. on ISPACS, pp. 57-60, 2009.
[12]A. S. Molahosseini et al., “Efficient MRC-Based Residue to Binary Converers for the New Moduli Sets {22n, 2n-1, 2n+1-1} and {22n, 2n-1, 2n-1-1},” IEICE Trans. on Inf. &; Syst., vol. E92. D, no. 9, pp. 1628-1638, 2009.
[13]A. S. Molahosseini et al., “A Reduced- Area Reverse Converter for the Moduli Set {2n, 2n-1, 22n-1-1},” Int. J. of Advan. in Comput.Technology, vol. 2, no. 5, pp. 61-65, 2010.
[14]K.A. Gbolagade et al., “Residue-to- Binary Converters for the Moduli Set {22n+1−1, 22n, 2n−1},” 2nd Int. Conf. on ICAST, pp. 26-33, 2009.
[15]A. Afsheh, et. al., An improved reverse converter for moduli set (2n−1, 2n, 2n+1), Intl. Symp. on Communications and Information Technologies, pp. 928-933, Oct. 2010.
[16]W. Wang, et. al., A high-speed residue-to-binary converter for three-moduli (2k, 2k-1, 2k-1-1) RNS and a scheme of its VLSI implementation, IEEE Trans. Circuits. Syst.II, vol.47. no. 12, pp. 1576-1581, 2000.
[17]M. Hosseinzadeh, et al., An improved reverse converter for the moduli set {2n−1, 2n, 2n+1, 2n+1−1},”IEICE Electronics Express, vol 5. no. 17, pp.672-677, 2008.
[18]W. Zhang et. al., An efficient design of residue to binary converter for four moduli set {2n-1, 2n+1, 22n-2, 22n+1-3} based on new CRT II, Elsevier J. Inf. Sci., pp. 264–279, 2008.
[19]Leonel Sousa and Samuel Antao, MRC-Based RNS Reverse Converter for the Four-Moduli Sets {2n+1, 2n-1, 2n, 22n+1-1} and {2n+1, 2n-1, 22n, 22n+1-1}, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 4, pp. 244-248, Apr. 2012.
[20]C. Efstathiou, H. T. Vergos, and D. Nikolos, Fast parallel-prefix modulo 2n+1adder, IEEE Trans. Comput., vol. 53, no. 9, pp.1211-1216, 2004.
[21]Y. Wang, X. Song, M. Aboulhamid, and H. Shen. “Adders based residue to binary numbers converters for (2n-1, 2n, 2n+1),” IEEE Trans. Signal Process., vol. 50, no. 7, pp. 1772-1779, Jul. 2002.
[22]A. Hiasat and A. Sweidan , “Residue number system to binary converter for the modili set (2n-1, 2n-1, 2n+1),” Elsevier J.Syst. Architect. vol. 49, pp. 53-58, 2003.
[23]Su-Hon Lin, Ming-Hwa Sheu, Chao-Hsiang Wang and Yuan-Ching Kuo, “Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1−1, 2n−1)” IEEE Asia Pacific Conference on Circuits and Systems. no. 30, pp. 168-171, Dec. 2008.
[24]Wang W, Swamy M.N.S, Ahmad M.O and Wang Y. “A study of the residue-to-binary converters for the three-moduli sets,” IEEE Trans. Circuits Syst. I, vol. 50, no. 2, pp.235-243, Feb. 2003.
[25]Su-Hon Lin, Ming-Hwa Sheu, Jing-Shiun Lin and Wen-Tsai Sheu, “Efficient VLSI design for RNS reverse converter based on new moduli set (22n+1, 2n+1,2n-1), ” IEEE Asia Pacific Conference on Circuits and Systems. pp. 2020-2023, Dec. 2006.
[26]K. A. Gbolagade, R. Chaves, L. Sousa and S. D, “An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set,” Proceedings of IEEE Int. Symp. on ISCAS, pp. 2103- 2106, 2010.
[27]A. Riyaz and B. Said, “Fast parallel-prefix architectures for modulo 2n-1 addition with a single representation of zero,” IEEE Trans on.Comput., vol. 56, no.11, pp.1484-1492, Nov. 2007.
[28]S. H. Lin, M. H. Sheu, C. H. Wang, and Y. C. Kuo, “Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1),” IEEE Asia Pacific Conf. Circuits and Systems, pp. 169-171, 2008.
[29]K.A. Gbolagade et al., “An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set,” IEEE Int. Symp. on ISCAS, pp. 2103- 2106, 2010.
[30]A .Hariri, K. Navi, and R. Rastegar. “A new high dynamic range moduli set with efficient reverse converter,” Elsevier Journal of Computers and Mathematics with Applications, vol. 55, issue 4, pp. 660-668, 2008.
[31]B. Cao, T. Srikanthan, and C. H. Chang, “Efficient reverse converter for the four-moduli sets {2n-1; 2n, 2n+1; 2n+1+1} and {2n-1, 2n, 2n+1, 2n-1-1},” Proc. IEE Comput. Digit. Tech., vol. 152, no. 5, pp. 687-696, Sep. 2005.
[32]P. V. A. Mohan, A. B. Premkumar, “RNS-to-Binary converters for two four-moduli sets {2n-1, 2n, 2n+1, 2n+1–1} and {2n-1, 2n, 2n+1, 2n+1+1},” IEEE Trans. Circuits Syst. I. vol. 54, no. 6, pp. 1245-1254, 2007.
[33]A.S. Molahosseini, F. Teymouri, and K. Navi, “A new four-modulus RNS to binary converter,” Proc. of IEEE Int. Symp. on ISCAS, pp. 4161- 4164, 2010.
[34]B. Cao, C. H. Chang, and T. Srikanthan, “An efficient reverse converter for the 4-moduli Set (2n-1, 2n, 2n+1, 22n+1) based on the new Chinese remainder theorem,” IEEE Trans. Circuits Syst. I, vol. 50, no. 10, pp. 1296–1303, Oct. 2003.
[35]A. S. Molahosseini, K. Navi, C. Dadkhah, O. Kavehei, and S. Timarchi, “Efficient reverse converter designs for the new 4-moduli sets {2n-1, 2n, 2n+1, 22n+1-1} and {2n-1, 2n+1, 22n, 22n+1} based on new CRTs,” IEEE Trans. Circuits Syst. I, vol. 57, no. 4, pp. 823-835, Apr. 2010.
[36]L. Sousa and S. Antao, “MRC-based RNS reverse converter for the four-moduli sets {2n+1, 2n-1, 2n, 22n+1-1} and {2n+1, 2n-1, 22n, 22n+1-1},” IEEE Trans. Very Large Scale Integer(VLSI) Syst., vol. 59, no. 4, pp. 244-247, Apr. 2012.
[37]W. Zhang and P. Siy, “An efficient design of residue to binary converter for four moduli set {2n-1, 2n+1, 22n-2, 22n-3} based on new CRT II,” Elsevier J. Inf. Sci., vol. 178, no. 1, pp. 264–279, Jan. 2008.
[38]R. Chaves, and L. Sousa. “{2n + 1, 2n+k, 2n - 1}: a new RNS moduli set extension,” Proc. of the Euromicro Symposium on Digital System Design, pp. 210-217, Sep. 2004.
[39]G. Chalivendra, V. Hanumaiah, and S. Vrudhula,, “A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient FIR filter implementation,” Proc. of the Great Lakes Symposium on VLSI, pp. 139-144, 2011.
[40]C. H. Chang and J. Low, “Simple, fast, and exact rns scaler for the three moduliset,” IEEE Trans. Circuits Syst I., vol. 58, no. 11, pp. 2686 –2697, November. 2011.
|