現今社會已經是數位化之時代，圖片壓縮JPEG亦已經是非常普遍之應用， 與此相關的研究亦不斷的出現，但是有研究文獻提出，大多數研究皆是專注於高速編碼器的設計上，並沒有從整體角度方向思考關於高速實時圖像編碼系統的設計與實現，且未來高張數的JPEG圖像壓縮更是重要。所以本文針對高速實時圖像編碼系統方面的研究，透過硬體設計思維以及記憶體特殊排列方式，再次進行改進與實現，達成僅使用三組壓縮於100MHz頻率下，完成最快時處理 (1080p)圖像150fps壓縮，亦或是最快時可以處理 (1MegaPixel)圖像300fps，以此來適應未來圖像壓縮需求。

It is the era of digitalization today, and the application of JPEG encoding has become very popular. Also, relative studies are being proposed continuously. Most of the studies focus on the design of high-speed encoder rather than that of high-speed JPEG image encoding system, which is more important. Therefore, this thesis presents a design of high-speed JPEG image encoding system which is base on FPGA. The encoder of this system could work in the pipeline mode and special reading and writing applications of Rams. Besides, The encoder of this system will support processing of 150fps for 1920 x1080(1080p) images, and the maximum speed could achieves 300fps for 1024x1024(1 Mega) images. As the frequency is 100MHz, the encoder core number is 3.

書名頁 ………………………………………………………………… i
論文口試委員審定書 ………………………………………………… ii
中文摘要 ……………………………………………………………… iii
ABSTRACT ……………………………………………………………… iv
誌謝 …………………………………………………………………… v
目錄 …………………………………………………………………… vi
圖目錄 ………………………………………………………………… vii
表目錄 ………………………………………………………………… ix
第一章、 序論…………………………………………………… 1
1.1 研究背景與動機 …………………………………… 1
1.2 相關文獻瀏覽 ……………………………………… 2
1.3 研究目標與方法 …………………………………… 3
1.4 論文架構 …………………………………………… 3
第二章、 FPGA方法與JPEG編碼介紹……………………… 4
2.1 FPGA (Filed Programmable Gate Array)方法介紹…… 4
2.2 JPEG壓縮……………………………………………… 6
第三章、 所提方法 ……………………………………………… 14
3.1 外部記憶體圖片配置方式…………………………… 14
3.2 流程架構……………………………………………… 14
3.2.1 影像進入內部記憶體配置步驟…………………… 15
3.2.2 二次一維離散餘弦轉換步驟 …………………… 17
3.2.2 量化與編碼記憶體配置步驟…………………… 18
第四章、 實驗結果………………………………………………… 21
4.1 實驗環境…………………………………………… 21
4.2 實驗結果討論……………………………………… 24
第五章、 結論與未來研究………………………………………… 28
參考文獻 ………………………………………………………… 29
自傳 ………………………………………………………… 30

參考文獻
[1] S. An and C. Wang, “Recursive Algorithm, Architectures and FPGA Implementation of the Two-dimensional Discrete Cosine Transform,” IET Image Process, Vol. 2, No. 6, pp. 286–294, December 2008.
[2] Liu Rui, Liu Peilin, and Zhao Hongxu, “Design and Implementation of High-Speed JPEG Image Encoding System Based on FPGA,” International Conference on Multimedia Technology, pp. 4887-4890, China, Hangzhou, July 2011.
[3] Enas Dhuhri Kusuma and Thomas Sri Widodo, “FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression,” International Symposium in Information Technology, pp. 1-6, June 2010.
[4] D. Trang and N. Bihn, “A High-Accuracy and High-Speed 2-D 8x8 Discrete Cosine Transform Design”, Proceedings of ICGCRCICT, Vol. 1, pp. 135-138, 2010.
[5] A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto, “A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs,” ISVLSI'07 IEEE Computer Society Annual Symposium, pp. 331-336, March 2007.
[6] JPEG Committee, “JPEG Homepage”, Available: http://www.jpeg.org/jpeg/index.html.
[7] R. Neelamani, R. de Queiroz, Z. Fan, S. Dash, and R. G. Baraniuk, “JPEG Compression History Estimation for Color Images” , IEEE Transactions on Image Processing, Vol. 15, No. 6, June 2006 , 1365-1378.
[8] Kishor Sarawadekar and Swapna Banerjee, “An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 21, No. 6, June 2011.