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參考文獻 [1] S. An and C. Wang, “Recursive Algorithm, Architectures and FPGA Implementation of the Two-dimensional Discrete Cosine Transform,” IET Image Process, Vol. 2, No. 6, pp. 286–294, December 2008. [2] Liu Rui, Liu Peilin, and Zhao Hongxu, “Design and Implementation of High-Speed JPEG Image Encoding System Based on FPGA,” International Conference on Multimedia Technology, pp. 4887-4890, China, Hangzhou, July 2011. [3] Enas Dhuhri Kusuma and Thomas Sri Widodo, “FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression,” International Symposium in Information Technology, pp. 1-6, June 2010. [4] D. Trang and N. Bihn, “A High-Accuracy and High-Speed 2-D 8x8 Discrete Cosine Transform Design”, Proceedings of ICGCRCICT, Vol. 1, pp. 135-138, 2010. [5] A. Tumeo, M. Monchiero, G. Palermo, F. Ferrandi, and D. Sciuto, “A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs,” ISVLSI'07 IEEE Computer Society Annual Symposium, pp. 331-336, March 2007. [6] JPEG Committee, “JPEG Homepage”, Available: http://www.jpeg.org/jpeg/index.html. [7] R. Neelamani, R. de Queiroz, Z. Fan, S. Dash, and R. G. Baraniuk, “JPEG Compression History Estimation for Color Images” , IEEE Transactions on Image Processing, Vol. 15, No. 6, June 2006 , 1365-1378. [8] Kishor Sarawadekar and Swapna Banerjee, “An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000”, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 21, No. 6, June 2011.
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