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研究生:莊浚志
研究生(外文):Chun-Chih Chuang
論文名稱:一個基於結構化客製晶片的靜態隨機存取記憶體編譯器和佈局單元資料庫
論文名稱(外文):Via Configurable Logic Block Design Oriented Toward Synthesis of SRAM
指導教授:林榮彬林榮彬引用關係
指導教授(外文):Rung-Bin Lin
口試委員:劉一宇董慧香
口試委員(外文):Yi-Yu LiuHui-Hsiang Tung
口試日期:2014-07-30
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:39
中文關鍵詞:靜態隨機存取記憶體結構化客製晶片佈局單元資料庫
外文關鍵詞:SRAMVia Configurable Logic Block DesignVCLB
相關次數:
  • 被引用被引用:0
  • 點閱點閱:309
  • 評分評分:
  • 下載下載:21
  • 收藏至我的研究室書目清單書目收藏:0
積體電路的製程越來越先進,在設計積體電路時要處理的問題也越來越困難。晶片製作需要多個的光罩,在製程越來越進步的情況下,光罩的費用也越來越昂貴。於是為了能夠降低晶片的成本,又能夠有很好的效能,結構化客製晶片的技術因而誕生。可程式化結構化客製晶片是由一些預製的電晶體,事先定義完成的金屬層,以及尚未定義的via 層(或少許的金屬層)組成。尚未定義的via 層是留給使用者來連接基本邏輯單元之間的連線及基本邏輯單元內的電晶體連線。基本邏輯單元由基本單元組成。一個好的基本單元必須要有高電晶體使用率且可符合各種不同需求的設計。記憶體是結構化客製晶片中的一個重要元件,其中最被廣泛的使用是靜態隨機存取記憶體。在本論文中,我們設計了一個VCLB不但可以提升SRAM效能,也可以維持實現邏輯電路的效能,我們利用所設計的VCLB建造了一個cell library,並用commercial tools來評估library跟之前本實驗室所設計的cell library比較,顯示以兩個cell library所合成的電路之delay、area、power都沒有太大的差異。最後,我們修改本實驗室之前一個SRAM compiler利用我們所設計的VCLB來產出SRAM IPs。
With the advancement of integrated circuit(IC) process, IC design issues that becomes complicate and difficult to handle. Since a chip consists of numerous pattern formational layers, mask cost becomes very large for an advanced manufacturing process. To reduce the cost of IC design and manufacturing, structured ASIC emerges as a new design alternative. A structured ASIC consists of some prefabricated transistors, prefabricated masks for some metal layers, and a couple of un-customized masks for vias (sometimes metal layers). A basic block for structured ASICs must provide powerful functional expression, high integration density, and flexibility to meet various application requirements. Memory IP is an important component for structured ASIC. One of the most widely used is the static random access memory (SRAM). In this thesis, we propose a via-configurable logic block (VCLB) which not only enhances the SRAM performance but also maintains the performance of logic circuits. We use our VCLB to create SRAM IPs and a cell library. Many of circuits synthesized based on our VCLB for building a SRAM have smaller area. We also evaluate our cell library by using it to synthesize some ITC99 benchmark circuits. We find that their area, delay, and power consumption are as good as that of the designs obtained by a cell library oriented logic design; We modify an SRAM compiler developed earlier to enable the use of our VCLB for synthesizing SRAM IPs
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Scope of The Work Contribution 4
1.4 Thesis Organization 5
Chapter 2. Related Work 6
2.1 Via Configurable Logic Block (VCLB) 6
2.2 Sequential, Combinational and Multi-Function Packed Block (MFPB) Cells 9
2.3 Basic CMOS Single-Port SRAM IP Design 10
2.4 Basic CMOS Dual-Port SRAM IP Design 12
Chapter 3. Proposed Work 13
3.1 Our Via Configurable Logic Block (VCLB) 13
3.2 Implementation of Single-port SRAM IP 14
3.2.1 Implementation of Memory Cell 14
3.2.2 Bit Line Conditioning Circuit 16
3.2.3 Clock Generator Circuit 17
3.2.4 Column Circuitry 18
3.2.4.1 Write Driver 18
3.2.4.2 Sense Amplifier 19
3.2.5 Column Multiplexer 20
3.2.6 Input Register 21
3.2.7 Tri-state Output Buffer 23
3.3 Implementation of Dual-Port SRAM IP 24
3.4 Structure of SRAM Compiler 25
3.4.1 Overview of SRAM Compiler 25
3.4.2 Layout Generator Flow 26
3.4.3 SPICE Netlist Generator 27
3.5 Layout of Single-port SRAM IP 28
3.6 Standard Cell Library Generation 29
Chapter 4. Experimental Results 31
Chapter 5. Conclusions 38
5.1 Our Conclusions 38
5.2 Future Work 38
References 39
[1] Zvi Or-Bach, "Paradiam Shift in ASIC Technology In-stand Metal Out-stand Cell", eASIC, 2006.
[2] Mei-Chen Li, Hui-Hsiang Tung, Chien-chung Lai, Rung-Bin Lin, “Standard Cell Like Via-Configurable Logic Block Design for Structured ASICs”, ISVLSI, pp. 381-386, 2008
[3] Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng, “Relocatable and Resizable SRAM Synthesis for Via Configurable Structured ASIC”, ISQED, pp.494-501, 2013
[4] Hsin-Pei Tsai, Rung-Bin Lin, and Liang-Chi Lai, “Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs”, DATE, pp.1479-1482, 2012
[5] Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, and Kuen-Wey Lin, “Power gating design for standard-cell-like structured ASICs”, DATE, pp.514-519, 2010
[6] Hui-Hsiang Tung, Rung-Bin Lin, Mei-Chen Li, and Tsung-Han Heish, “Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20, Issue: 12), pp.2184-2197, 2012
[7] Ashish Karandikar, Keshab K. Parhi, “Low Power SRAM Design using Hierarchical Divided Bit-Line Approach”, ICCD, pp.82-88, 1998.
[8] Tsung-Han Heish, Rung-Bin Lin, “Implementation of OpenRISC 1200 Based SoC Platform using Via-Configurable Structured ASICs”, Master Thesis, Yuan Ze University, Taiwan, 2011.
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