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研究生:吳宣融
研究生(外文):Shiuan-Rung Wu
論文名稱:被動式超高頻RFID感知器之數位控制電路設計
論文名稱(外文):Digital Controller for Passive EPC-Gen2 UHG RFID Sensor
指導教授:吳紹懋
指導教授(外文):Sau-Mou Wu
口試委員:林書彥江正雄劉榮宜
口試委員(外文):Shu-Yan LinJheng-Syong JiangRong-Yi Liou
口試日期:2014-01-14
學位類別:碩士
校院名稱:元智大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:英文
論文頁數:120
中文關鍵詞:RFIDEPC-Gen2 UHF
外文關鍵詞:RFIDEPC-Gen2 UHF
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本論文提出一個被動式超高頻RFID溫度感知器之控制器子系統設計,本子系統符合EPC Gen2規格,包括解碼器和編碼器,以及EPC Gen2的通訊協定,並以自訂之handshaking方式與無線感知器的RF前端系統溝通,以將感知器測得的溫度回傳至讀取端。本子系統最初以Verilog設計,經轉換為FPGA驗證無誤後,再以臺積電0.18 um 標準製程之ASIC實現,最終再用Agilent v93000 ps1600測試,並與無線感知器的RF前端系統整合測試。晶片布局面積為 1.1x1.1 mm2 ,實驗顯示出其資料傳輸速率從40kbps到640kbps,編碼器支援FM0格式或Miller格式。
In this thesis, a passive UHF RFID temperature sensor controller is presented. This system is complied with EPC Gen2 specifications, including decoder, encoder, and sensor interface control. In particular, a customized handshaking mechanism is defined to support the communication between the temperature sensor and the RF frontend such that the result from the temperature sensor can be transmitted to the reader by the load modulation mechanism. The subsystem is initially designed in Verilog, and verified with FPGA board. Afterwards, the system is implemented as an ASIC in the standard TSMC 0.18 um MM/RF CMOS 1P6M process. The chip area is about 1.1 x 1.1 mm2 and is measured with Agilent V93000 ps1600. At the end, it is integrated with the RF frontend chip on the PC-board level and tested. Experimental results show that data rate range from 40 to 640kbps. The data format can be in either FM0 or Miller patterns.
Chinese Abstract………………………………………………………………….……………………………..i
English Abstract …………………………………………………………………………………………………ii
Acknowledgement…....……………………………………………………………………………………..iii
List of Contents.....…………………………………………………………………………………………….iv
List of Table………………………………………………………………………………………………………vii
List of Figure……………………………………………………………………………………………………..ix

Chapter 1 Introduction 1
1.1 Background and Applications 1
1.1.1 The Architecture of RFID System 3
1.1.2 The Communication Model of RFID System 6
1.2 Motivation 7
1.3 Thesis Organization 8
Chapter 2 Proposed System Overview 9
2.1 Analog to Digital Data 9
Chapter 3 System Architecture and Theories 13
3.1 Communication protocol 13
3.2 Standard of EPC Gen2 Communications 15
3.3 Dual Clocking Scheme 19
Chapter 4 Building Block Design, Analysis and Simulations 21
4.1 Basic Digital Backend 21
4.2 PIE Decoder 22
4.3 CRC5 & CRC16 26
4.4 Encoder 29
4.4.1 Backscatter 30
4.4.2 FM0 Encoder 32
4.4.3 Miller Encoder 36
4.5 Memory 42
4.6 Random Number Generator 44
4.7 Interface with Sensor 46
4.8 Command Handler FSM 50
4.8.1 Functional Description and Tag State 50
4.8.1.1 Slot Counter 52
4.8.2 Interrogator Commands and Tags Replies 55
4.8.2.1 Query 55
4.8.2.2 QueryAdjust 57
4.8.2.3 QueryRep 59
4.8.2.4 ACK 60
4.8.2.5 NAK 60
4.8.2.6 Req_RN 61
4.8.2.7 Read 62
4.8.2.8 Write 64
4.8.2.9 Kill 65
4.8.3 FSM simulation 66
Chapter 5 Testing and Experimental Results 68
5.1 FPGA testing and implementation 68
5.2 FPGA Function Testing 69
5.2.1 PIE decoder 69
5.2.2 Encoder 71
5.2.2.1 FM0 encoder 71
5.2.2.2 Miller encoder 72
5.2.3 CRC-5 and CRC-16 76
5.2.4 Random number generator 78
5.2.5 All the Command Test 78
5.3 Chip Specification 80
5.4 Testing Environment 81
5.4.1 Result of Measurement 85
5.4.2 Shmoo Plot 98
Chapter 6 Conclusion and Future Work 99
6.1 Conclusion 99
6.2 Future Work 100
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