臺灣博碩士論文加值系統

近年來，隨著製程的進步，越來越多硬體應用整合在同一塊晶片上。晶片上的處理單元借由平行運算來加速整體效能，傳統上，處理單元使用單一條匯流排來進行資料傳輸，然而這卻可能造成傳輸上的瓶頸，為了支援更有效率的溝通，晶片網路作為提高傳輸平行度的架構被提了出來。在晶片網路的架構下，應用程式的任務會被分派給其相應的硬體應用去執行，在分派完成之後，該硬體應用便不能再讓其他應用程式作使用，直到原本在上面的任務執行結束，然而，當應用程式取得這塊硬體應用到它執行結束，期間不一定會每時每刻地去使用它，這可能導致運算資源的浪費，為了解決這個議題，我們提出了一個軟體導向的虛擬化晶片網路架構 (Virtualization Architecture for Application-Oriented Network-on-Chip，簡稱VNoC)，VNoC為一個3 X 3的晶片網路架構，每個硬體應用包含一個路由器與其它硬體應用互相連接，我們的設計對硬體應用進行了虛擬化，它主要是使得同一個硬體應用借由分時處理的機制，能在同一個時間點下去服務兩個應用程式。為了更進一步提高硬體的使用彈性，我們的設計結合了硬體可重組式的功能，使得每個硬體應用能在系統執行時被動態重組成其它的硬體，而其餘硬體可以不受到影響。我們在Xilinx Virtex-6 的FPGA上實作我們的VNoC雛型架構。實驗和評估顯示，我們提出的架構比起常規的晶片網路架構能夠提高平均42\%左右的效能，而在硬體資源的使用上比起常規的架構，只多使用了約3\%左右的組合邏輯資源。

Due to advances in technology, more and more processing elements (PEs) are integrated into a single chip such that computations can be performed in parallel. However, the PEs are inter-connected by a communications bus, that could become a data transfer bottleneck. To alleviate this bottleneck, Network-on-Chip (NoC) was proposed as an alternative interconnection architecture. In the NoC architecture, when an application task is mapped to a PE, this PE is thus blocked and cannot be used by other application tasks, until the previous application finishes. However, in fact, the PE is not used by the application all the time. This would lead to a waste of computing resources. To solve the above issue, this work proposes a virtualization architecture for application-oriented NoC systems (VNoC). The VNoC was implemented as a $3 \times 3$ mesh NoC architecture. PEs on the VNoC have a router to connect each other. The VNoC design makes a single PE can service two application tasks at the same time. To improve the hardware flexibility, we integrated the reconfiguration design in our system. So that the PE on the VNoC can be dynamically reconfigured to the other IP and the remaining hardware IPs are unaffected. We implemented the proposed VNoC design on the Xilinx Virtex-6 FPGA device. Experiment results show that our architecture compared to the conventional NoC can exhibits performance improvement by 42\%. The additional resource usage for VNoC on the target FPGA is around 3\% of the available slice LUTs.

1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Bus and Network-on-Chip Interconnection . . . . . . . . . . . 2
1.1.2 Reconfigurable Design . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Related Work 9
2.1 NoC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Reconfigurable NoC Architectures . . . . . . . . . . . . . . . . . . . . 11
2.3 Virtual NoC Architectures . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Preliminaries 16
3.1 NoC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 Router Architecture . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.3 Routing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.4 Network Interface . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Partial Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4 Virtualization Architecture Design 23
4.1 Packet Format of the VNoC . . . . . . . . . . . . . . . . . . . . . . . 23
4.2 Router Design for VNoC . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 Virtualization Controller Design . . . . . . . . . . . . . . . . . 28
4.3 Network Interface Design for VNoC . . . . . . . . . . . . . . . . . . . 29
4.4 PE Wrapper Design for VNoC . . . . . . . . . . . . . . . . . . . . . . 32
4.5 Sequential Packets of the Application Task . . . . . . . . . . . . . . . . 33
4.6 Usage of PE Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.7 PE Sender design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.8 Global Manager for VNoC . . . . . . . . . . . . . . . . . . . . . . . . 38
4.9 VNoC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.10 VNoC Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5 Experiments 43
5.1 Experimental Framework . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2 Function Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2.1 The Function with Single Input Packet . . . . . . . . . . . . . . 44
5.2.2 The Function with Multiple Input Packets . . . . . . . . . . . . 47
5.3 VNoC Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.4 Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6 Conclusions and Future Work 52
Bibliography 53

[1] L. Benini and G. De Micheli. Networks on chips: a new SoC paradigm. Computer,35(1):70--78, Janunary 2002.
[2] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A network on chip architecture and design methodology. In Proceedings IEEE Computer Society Annual Symposium on VLSI, pages 105--112,
April 2002.
[3] F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost. Hermes: an infrastructure for low area overhead packet-switching networks on chip. INTEGRATION, the VLSI journal, 38(1):69--93, October 2004.
[4] L.M. Ni and P.K. McKinley. A survey of wormhole routing techniques in direct networks. Computer, 26(2):62--76, February 1993.
[5] D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw. A highly resilient routing algorithm for fault-tolerant nocs. In Proceedings of the Conference on Design, Automation and Test in Europe, pages 21--26. European Design and Automation Association, March 2009.
[6] T. Dorta, J. Jimenez, J.L. Martin, U. Bidarte, and A. Astarloa. Overview of FPGAbased multiprocessor systems. In Proceedings of the Reconfigurable Computing and FPGAs., pages 273--278, December 2009.
[7] E.L. Horta, W.L. John, D.E. Taylor, and D. Parlour. Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In Proceedings of the 39th Annual Design Automation Conference, pages 343--348. ACM, June 2002.
[8] D. Coppersmith. The data encryption standard (DES) and its strength against attacks. IBM Journal of Research and Development, 38(3):243--250, April 1994.
[9] J. Daemen and V. Rijmen. The design of Rijndael: AES-the advanced encryption standard. Springer Science & Business Media, December 2002.
[10] R. Nair, G. Ryan, and F. Farzaneh. A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC). In Proceedings of the VHDL International Users' Forum., pages 82--87. IEEE, October 1997.
[11] J. Liang, S. Swaminathan, and R. Tessier. asoc: A scalable, single-chip communications architecture. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 37--46. IEEE, October 2000.
[12] C.A. Zeferino and A.A. Susin. SoCIN: a parametric and scalable network-on-chip. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, pages 169 -174, September 2003.
[13] R.J. Fong, S.J. Harper, and P.M. Athanas. A versatile framework for FPGA field updates: an application of partial self-reconfiguration. In Proceedings of the 14th IEEE International Workshop on Rapid Systems Prototyping, pages 117--123.
IEEE, June 2003.
[14] L. Möller, I. Grehs, E. Carvalho, R. Soares, N. Calazans, and F. Moraes. Anocbased infrastructure to enable dynamic self reconfigurable systems. pages 1--4, August 2006.
[15] T. Marescaux, J.-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde, and R. Lauwereins. Networks-on-chip as hardware components of an OS for reconfigurable systems. In Proceedings of the International Conference on Field Programmable Logic and Application, pages 595--605. Springer, Setempter 2003.
[16] Z. Zhang, A. Greiner, and S. Taktak. A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip. In Proceedings of the 45th ACM/IEEE on Design Automation Conference, pages 441--446. IEEE, June 2008.
[17] C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J. van der Veen. DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices. In Proceedings of the International Conference on Field Programmable Logic and Applications, pages 153--158. IEEE, August 2005.
[18] M.B. Stensgaard and J. Sparso. ReNoC: A network-on-chip architecture with reconfigurable topology. In Proceedings of the Second ACM/IEEE International
Symposium on Networks-on-Chip, pages 55--64. IEEE, April 2008.
[19] T.A. Bartic, J.-Y. Mignolet, V. Nollet, T. Marescaux, D. Verkest, S. Vernalde, and R. Lauwereins. Highly scalable network on chip for reconfigurable systems. In
Proceedings of the International Symposium on System-on-Chip, pages 79--82. IEEE, November 2003.
[20] L. Möller, I. Grehs, N. Calazans, and F. Moraes. Reconfigurable systems enabled by a Network-on-Chip. In Proceedings of the International Conference on Field Programmable Logic and Applications, pages 1--4. IEEE, Auguest 2006.
[21] I.M. Panades, A. Greiner, A. Sheibanyrad, and G. STMicroelcctronics. A low cost network-on-chip with guaranteed service well suited to the gals approach. Stempter 2006.
[22] J. Kwa and T.M. Aamodt. Small virtual channel routers on FPGAs through block RAM sharing. In Proceedings of the International Conference on Field-
Programmable Technology, pages 71--79. IEEE, December 2012.
[23] A. Kostrzewa, S. Tobuschat, P. Axer, and R. Ernst. Supervised sharing of virtual channels in networks-on-chip. In Proceedings of the 9th IEEE International Symposium on Industrial Embedded Systems, pages 133--140. IEEE, June 2014.
[24] A. Kumar, L.-S. Peh, P. Kundu, and N.K. Jha. Express virtual channels: towards the ideal interconnection fabric. In ACM SIGARCH Computer Architecture News, volume 35, pages 150--161. ACM, May 2007.
[25] X. Fu, T. Li, and J. Fortes. Reliable express-virtual-channel-based network-onchip under the impact of technology scaling. In Proceedings of the International
Symposium on Quality Electronic Design (ISQED), pages 719--726. IEEE, March 2013.
[26] C.J. Glass and L.M. Ni. The turn model for adaptive routing. In ACM SIGARCH Computer Architecture News, volume 20, pages 278--287. ACM, May 1992.
[27] Partial Reconfiguration User Guide. Ug702 (v13. 1). Available in http://www. xilinx. com/support/documentation/sw_manuals/xilinx13_1/ug702. pdf, April 2013.
[28] J.-S. Shen, C.-H. Huang, and P.-A. Hsiung. Learning-based adaptation to applications and environments in a reconfigurable network-on-chip. In Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 381--386. IEEE, March 2010.
[29] R. Fielding, J. Gettys, J. Mogul, H. Frystyk, L. Masinter, P. Leach, and T. Berners- Lee. Hypertext transfer protocol--HTTP/1.1. RFC 2616, June 1999. http:// www.rfc-editor.org/rfc/rfc2616.txt.
[30] J. Postel and J. Reynolds. File transfer protocol. STD 9, October 1985. http://
www.rfc-editor.org/rfc/rfc959.txt.
[31] A.C. Weaver. Secure sockets layer. Computer, 39(4):88--90, April 2006.
[32] A. Freier, P. Karlton, and P. Kocher. The secure sockets layer (SSL) protocol version 3.0. RFC 6101, August 2011. http://www.rfc-editor.org/rfc/rfc6101.txt.