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研究生:蘇國禎
研究生(外文):SU,KUO-CHEN
論文名稱:針對多媒體應用之新穎的快取架構
論文名稱(外文):A Novel Cache Architecture for Multimedia Applications
指導教授:張榮貴張榮貴引用關係
指導教授(外文):CHANG,RONG-GUEY
口試委員:薛智文張榮貴陳鵬升羅習五
口試委員(外文):HSUEH,CHIH-WENCHANG,RONG-GUEYCHANG,PENG-SHENGLO,SHI-WU
口試日期:2016-07-11
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2016
畢業學年度:103
語文別:英文
論文頁數:27
中文關鍵詞:gem5快取mediabench II區塊分割演算法
外文關鍵詞:gem5cachemediabench IIblock-based algorithm
相關次數:
  • 被引用被引用:0
  • 點閱點閱:122
  • 評分評分:
  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
本論文題出一個嶄新的快取架構專注於改善多媒體應用在第一層資料快取的失誤率。我們分析多媒體應用的特性,發現多媒體應用的演算法多數都基於以固定大小的區塊為處理單位,因此我們利用這個特性改善快取的失誤率。

以區塊做為處理單位的記憶體進出模式在傳統的快取架構中造成大量的碰撞失誤。本論文提出一個新的快取架構藉由盡可能地保留區塊在快取中並降低碰撞失誤的發生,我們分析區塊的記憶體進出模式並且將符合這個記憶體進出模式的資料保留在快取中以提高快取命中率。本論文提出的架構會將區塊盡可能地分散到不同的子快取中以降低同一個集合下過度存取所造成的碰撞失誤,防止整個區塊的快取資料在短時間內被完全取代掉。

我們的方法實作在Gem5模擬器上並且使用ARM指令集與亂序執行的CPU模型去模擬mediabench II上的快取的失誤率。實驗結果顯示平均每筆benchmark可以改善33.3% 。

In this thesis, we focus on improving level-1 data cache miss rate by the new cache architecture that we proposed for multimedia applications. Multimedia applications generally based on the block-based algorithm with a fixed block size.

The memory access pattern of the block-based algorithm will cause amounts of conflict misses in conventional cache architecture. This thesis will present an approach for reducing cache miss rate by keeping the memory access pattern of block and allocating the data fit in with the memory access pattern to different sub-caches. Cache data is classified according to its tag address in our approach and the approach can avoid the entire block be replaced when cache suffers from large amounts of conflict misses.

The approach is implemented on Gem5 simulator and running on MediaBench II which includes popular multimedia applications in recent for test suite. The performance resulted in an average reduction to 33.3 percent executed on out-of-order processor with ARM instruction sets.

1. Introduction.....................1

2. Related work.....................4

3. Basic Idea.......................6

4. The Proposed Approach...........10

5. System Architecture.............13

6. Conclusions and future work.....16

7. Reference.......................22

[1] Zhiyong Xu, Sohum Sohoni,Rui Min, and Yiming Hu.
An analysis of cache performance of multimedia applications.
IEEE Transactions on Computers, vol.53, pp.20-38,2004.

[2] Ye Gao,Naoki Shoji,Ryusuke Egawa,Hiroyuki Takizawa,and Hiroaki Kobayashi.
Design and evaluation of a media-oriented vector processor with a multi-banked cache memory.
The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, pp. 78-87, 2013.

[3] Abu Asaduzzaman,Vidya R.Suryanarayana,and Mizan Rahman.
Performance-power analysis of H.265/HEVC and H.264/AVC running on multicore cache systems.
Intelligent Signal Processing and Communications Systems (ISPACS), 2013 International Symposium on, pp. 174-179, 2013.

[4] Xie Yuejian,Zhang Youhui,and Wang Dongsheng.
Heterogeneous Associative Cache for Multimedia Applications.
Internet and Multimedia Systems and Applications, EuroIMSA 2007

[5] V. Milutinovic, M. Tomasevic, B. Markovi, and M. Tremblay
A new cache architecture concept: the split temporal/spatial cache
Electrotechnical Conference, 1996. MELECON '96, 8th Mediterranean, 1108 - 1111 vol.2, 1996

[6] P. Ranganathan, S. Adve , and N. P. Jouppi.
Reconfigurable caches and their application to media processing
Computer Architecture.
Proceedings of the 27th International Symposium on, pp. 214–224, 2000.

[7] Junghee Lee, Chanik Park, and Soonhoi Ha.
Memory access pattern analysis and stream cache design for multimedia applications.
Design Automation Conference. Proceedings of the ASP-DAC 2003. Asia and South Pacific, pp. 22–27, 2003.

[8] J. A. Rivers, G. S. Tyson, and E. S. Davidson, and T. M. Austin
On High-Bandwidth Data Cache Design for Multi-Issue Processors
Microarchitecture, 1997. Proceedings, Thirtieth Annual IEEE/ACM International Symposium on, pp. 46–56, 1997.

[9] Nathan Binkert1 , Bradford Beckmann2 , Gabriel Black3 , Steven K. Reinhardt2 , Ali Saidi4 , Arkaprava Basu5 , Joel Hestness6 , Derek R. Hower5 , Tushar Krishna7 , Somayeh Sardashti5 , Rathijit Sen5 , Korey Sewell8 , Muhammad Shoaib5 , Nilay Vaish5 , Mark D. Hill5 , and David A. Wood.
The gem5 Simulator.
ACM SIGARCH Computer Architecture News archive, Volume 39 Issue 2, Pages 1-7, 2011.

[10] G. K. Wallace.
The JPEG still picture compression standard.
IEEE Transactions on Consumer Electronics, vol. 38, 2002

[11] T. Sikora.
MPEG digital video-coding standards.
IEEE Signal Processing Magazine vol. 14, pp. 82–100, 2002.

[12] T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra.
Overview of the H.264/AVC video coding standard.
IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, pp. 560–576, 2003.

[13] Jason E. Fritts, Frederick W. Steiling, Joseph A. Tucek, and Wayne Wolf.
MediaBench II video: Expediting the next generation of video systems research.
Journal Microprocessors & Microsystems archive, vol. 33, pp. 301-318, 2009

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