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研究生:黃士杰
研究生(外文):Shih-Chieh Huang
論文名稱:閉迴路式高度整合無線CMOS金屬鎊線加速度計晶片設計
論文名稱(外文):A Closed-Loop, Fully-Integrated Wireless CMOS Bondwire Accelerometer Design
指導教授:廖育德蔡宗亨蔡宗亨引用關係
指導教授(外文):Yu-Te LiaoTsung-Heng Tsai
口試委員:鐘菁哲
口試委員(外文):Ching-Che Chung
口試日期:2014-10-13
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:103
語文別:英文
論文頁數:81
中文關鍵詞:加速度計金屬鎊線
外文關鍵詞:AccelerometerBondwire
相關次數:
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針對老年人口比例逐年增長、高齡化社會的趨勢,老年人的健康照護已逐年受到重視,學術界、業界與政府皆極力推廣健康照護系統。其中,加速度計由於具備微型化、響應快、低功耗並且易於攜帶,現今已被廣泛運用於紀錄人體活動。
本篇論文提出新型高度整合之無線加速度計,並以金屬鎊線當作感測電路而不使用較為昂貴且複雜的微機電製程。論文中使用有限元素方法模擬軟體建立並探討金屬鎊線模型的長度與高度對於不同加速度值所造成的變化。此外,本論文提出了以鎖相迴路為解調變架構。和過去的加速度計讀出電路架構比較,此架構具有低功耗與受環境變異影響度低的優點。
此金屬鎊線加速度計晶片採用TSMC 0.18 μm 製程,晶片面積為2×2.39 mm^2。鎖相迴路在距離中心頻率1 MHz之相位雜訊為 -117.1 dBc/Hz,KVCO為3.8 MHz/V。此加速度計的增益為6 mV/g的線性增益(在低雜訊放大器前)。整體的功率消耗為9 mW的功率消耗。低雜訊放大器的可調增益為13.1到27.8 dB,數位類比轉換器的有效位元數為8.1 bits,並整合無線傳輸(OOK/ASK)於單一晶片中。量測兩條直徑為0.6 mil與1 mil的金屬鎊線之共振頻率分別為5.92 KHz 與10.6 KHz。量測金屬鎊線加速度計的可用頻寬為5 KHz、雜訊水平為10.6 μg/sqrt(Hz)。整體的頻寬受限於細的金鎊線的機械共振頻率。此外,在迴路鎖定中心頻率為2.4 GHz的情況下,迴路頻寬內所量測到的訊號雜訊比大於30 dB。

The population of over 65-year ages is one of the major portions in the world’s population and is expected to increase dramatically in the nearly few decades. The cost of elder’s care has been a large burden in the developed countries. To enhance the living quality, development of remote and self-living healthcare systems attracts the focuses from industries, academia, and government. For the elders’ care, one of the most important health indexes is the human daily activity. Wireless sensor systems with integrated accelerometers have been adopted as standard devices to recognize and record the human activities continuously during their daily life.
This thesis presents a fully-integrated CMOS accelerometer using bondwires as sensing devices without expensive MEMS processes. A precise bondwire model is demonstrated in this work using the FEM simulation. Besides, a PLL-based demodulation architecture is proposed to reduce the design complexity, power consumption, and the frequency drifts caused by environment.
The bondwire accelerometer was implemented in a TSMC 0.18 μm CMOS process. The chip size is 4.78mm^2 (2×2.39 mm^2). The design achieves a linear transducer gain of 6 mV/g before amplification while consuming 9 mW. The measured LNA gain ranges from 13.1 dB to 27.8 dB. The measured ENOB of ADC is 8.1 bits. Besides, the system is integrated with PA for wireless data transmittion (OOK/ASK). The measured phase noise of PLL is -117.1 dBc/Hz at 1MHz offset from the center frequency (2.4 GHz), and the measured KVCO is 3.8 MHz/V. The measured resonant frequencies of 0.6-mil and 1-mil bondwire sensors are 5.92 KHz and 10.6 KHz, respectively. The measured accelerometer bandwidth is 5 KHz, which is limited by the mechanical resonant frequency of the thin bondwire. In addition, the measured noise floor of accelerometer is 10.6 μg/sqrt(Hz). Within the frequency span of 100 KHz from 2.4 GHz (center frequency of this design), the measured signal to noise ratio is larger than 30 dB.

摘要
Abstract
Contents
FIGURE CAPTIONS
TABLE CAPTIONS
Chapter 1 Introduction
1.1 Motivation of Research
1.2 Current Studies on Accelerometers
1.3 Research of CMOS-MEMS Process
1.4 Solution and Research Goal
1.5 Thesis Organization
Chapter 2 Model and Analysis of Bondwire Sensor
2.1 Bondwire Modeling
2.1.1 Effects of the Bondwire Diameters and Lengths of Acceleration Sensors
2.1.2 Effects of the Bondwire Height of the Acceleration Sensors
2.2 Resonant Frequency of Bondwires
2.3 Package and Variation of Bondwire Sensor
Chapter 3 System Design of Bondwire Accelerometer
3.1 FM Demodulator
3.1.1 Types of FM Demodulators
3.2 Noise Analysis of Phase-Locked Loop
3.2.1 Noise of Voltage-Controlled Oscillator
3.2.2 Noise of Reference
3.2.3 Noise Contributions on a PLL
Chapter 4 CMOS Accelerometer Using Bondwire Oscillator Sensor
4.1 Prior Arts of Bondwire Accelerometer
4.2 Behavior model of Phase-Locked-Loop
4.3 Circuit Design
4.3.1 Phase and Frequency Detector Circuit Design
4.3.2 Charge Pump Circuit Design
4.3.3 Second Order Loop Filter Design
4.3.4 Voltage Controlled Oscillator Circuit Design
4.3.5 Frequency Divider Circuit Design
4.3.6 Low Noise Amplifier Circuit Design
4.3.7 Power Amplifier Circuit Design
4.3.8 Regulator Circuit Design
4.4 Analog to Digital Converter Circuit Design
4.4.1 Sample and Hold Circuit Design
4.4.2 Comparator Design
4.4.3 Digital to Analog Converter
4.4.4 Successive Approximation Register and Control Logic
4.4.5 SAR-ADC System Simulation Results
Chapter 5 Chip Implementation and Measurement Results
5.1 Measurement Results of Bondwire Model
5.2 Measurement Results of the PLL system and ADC
5.3 Measurement Results of Bondwire Accelerometer Sensor
Chapter 6 Conclusion and Future Work
Reference

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