臺灣博碩士論文加值系統

調降電壓早已成為CMOS電路提升能源使用效率之重要手段；而使用即時即地(in-situ)時序錯誤感知與校正設計技術(包含需要錯誤更正週期的Razor與TDTB等技術與不需要更正週期的TBLB技術)，更可加深調降電壓幅度，以節省更多功率消耗。然而傳統上，上述設計一般是根據最差工作條件(worst operating condition)來進行設計的，使用過多高速但耗電的元件細胞，即使降低電壓回收之能源還是有限；故能源使用效率的角度來看，仍然留有相當大的改善空間。這個問題，對於如物聯網等需要極高能源使用效率的應用設計核心—微控制器核(MPU Core)而言，尤其顯得重要。
本研究以具有極大製程變異之28nm CMOS製程下之openMSP430設計為例，提出對於上述問題的改善方案。重要的設計技術包括：
(1) 使用一般工作條件(typical operating condition)進行設計，目的是想要進一步節省在一般狀態操作時電路面積並降低主動(active)與等待(standby)功率消耗。
(2) 使用即時即地時序錯誤感知與錯誤校正設計技術，來解決電路面臨工作條件變差而無法正常工作之問題。
(3) 使用不需要錯誤更新週期的TBLB技術來搭配管線深度僅有3級之MSP430(註：需要錯誤更新週期的Razor與TDTB等技術並不適用於僅有3級之MSP430)，同時避免更新架構之設計代價，並保持指令執行之連續性。
(4) 提出預先提升電壓(pre-boost)技術來解決最後一級memory管線無法使用TBLB技術之限制。
(5) 透過系統性指令分析，進行”選擇性pre-boost電路”設計，以降低TBLB技術中電壓提升控制電路之複雜度及縮短電壓提升時間。
(6) 有別於傳統電壓探底技術僅可行於模擬階段，本設計由於pre-boost設計技術，使得工作中(run-time)自動追求電壓探底工作變得可行。
(7) 提出完整設計流程，以正確比較"最差工作條件式"與"一般工作條件式"兩種設計之整體表現，以期能將本研究所提出之設計方法推展至其他種類設計。

實際設計與模擬數據顯示，相對於傳統最差工作條件設計，本新型設計除了達到4%面積節省外，於一般工作條件下節省了35%功率消耗，而在最差條件需要9%額外功率消耗(相對電壓較高)仍可正常操作。

Lowered voltage has become an important method to enhance the energy efficiency of CMOS circuits. Incorporates in-situ error detection and correction mechanism to recover from timing errors (including the need for error correction cycle Razor and TDTB technique and does not require correction cycle TBLB technique), but also scale down the range of voltage, to save more power consumption. Traditionally, however, the above design is generally based on worst operating conditions to design, while using too much high speed but large power consumption element cells, even lowering supply voltage to recycling energy is still limited; therefore energy efficiency of the use of perspective, still leaves considerable for improvement. This issue needs for Internet of things such as high energy efficiency using an application core design - microcontroller core, it is especially important.
This thesis, designed openMSP430 under great process variability of 28nm CMOS technology, for example, proposed to improve the above problems. Significant design technique includes:
(1) Using the typical operating condition to design, our purpose is to save circuit area and want to further reduce the active and standby power consumption
(2) Using in-situ timing error detection and correction design techniques to solve problems facing the the working conditions deteriorate and the circuit does not work.
(3) Useing does not require error correction cycle TBLB technique to match the level of the pipeline depth is only 3 MSP430 (Note: Need error correction cycle Razor and TDTB technique does not apply to just a level of 3 MSP430), while avoiding the architecture of design updates the cost and maintain the continuity of instruction execution.
(4) Proposed pre-boost technique to solve the limitation of the last Memory stage of the pipeline cannot be used TBLB technique.
(5) Through systematic instruction analysis, "conditional pre-boost circuit" is designed to reduce TBLB technique voltage boost control circuit complexity and shorten the voltage rise time.
(6) Unlike traditional voltage dip technique it is only feasible in the simulation stage, the design since the pre-boost technique, making the run-time automatic voltage dip pursue work has become feasible.
(7) Proposes a complete design flow in order to properly compare "worst case" and "typical case" overall performance of the two designs, in order to be able to propose the design method of this study be extended to other types of designs.

The actual design and simulation data shows, as opposed to worst case design, this new design in addition to 4% area savings, under normal operating conditions in the solution save power consumption by 35%, and 9% in the worst operating conditions require extra power consumption (relatively a higher voltage) to continue its normal operations..

目錄
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 本論文之章節介紹 2
第二章 適應性動態電壓調變技術 4
2.1 傳統worst case設計 4
2.2 AVS系統設計分析 4
2.1.1 AVS系統設計概念 5
2.1.2相關 AVS系統設計 6
2.3 TBLB CMOS 10
2.3.1 TBLB CMOS系統架構 11
2.3.2 TBLB CMOS時序分析 13
2.3.3 短路徑時序限制(Short Path Constraint) 15
2.3.4 AVS系統比較與總結 17
2.4 Typical case電路設計 10
2.4.1 Typical case電路系統設計概念 18
2.4.2 AVS系統應用於Typical case電路設計 20
第三章 適應性動態電壓調變技術應用於MSP430之分析 21
3.1 MSP430微處理器介紹 21
3.2 MSP430指令與路徑分析 21
3.2.1 MSP430指令集介紹 24
3.2.2 MSP430指令執行行為與關鍵路徑分析 26
3.3 TBLB-BASED MSP430 31
第四章 TBLB在MSP430之限制與預先升壓機制 34

4.1 AVS系統中路經概念 34
4.2 MSP430無法出錯的路徑 35
4.3 MSP430與預先升壓機制 38
4.3.1 預先升壓機制 38
4.3.2 選擇性預先升壓機制 40
第五章 可感知變異與高能源效率技術實現於MSP430實現方法 45
5.1 Worst case環境下實作MSP430 45
5.1.1 傳統worst case實作流程與結果 45
5.1.2 TBLB系統實作流程與結果 46
5.1.3 TBLB系統與預先升壓機制實作流程與結果 50
5.2 Typical case環境下實作MSP430 53
5.2.1 TBLB系統實作流程與結果 55
5.2.2 TBLB系統與預先升壓機制實作流程與結果 57
5.3 WC與TC情況設計下的整體分析與總結 59
第六章 總結與未來研究方向 62
參考文獻 66
附錄 68

參考文獻
[1]D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D.Blaauw, T.Austin, K. Flautner, and T. Mudge, “Razor: a low power pipeline based on circuit level timing speculation,” in Proc. Int. Symp. Microarchitecture (MICRO-36), Dec. 2003, pp. 7–18.
[2]S.Das,D.Roberts,S.Lee,S.Pant,D.Blaauw,T.Austin,K.Flautner, and T. Mudge, “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.792–804, Apr. 2006.
[3]S.Das,C.Tokunaga,S.Pant,W.-H.Ma,S.Kalaiselvan,K.Lai,D.M.Bull, and D. T. Blaauw, “Razor II: In situ error detection and correction for PVT and SER tolerance,” IEEE J. Solid-State Circuits, vol. 44, no.1, pp. 32–48, Jan. 2009.
[4]K.A.Bowman,J.W.Tschanz,N.S.Kim,J.C.Lee,C.B.Wilkerson,S.-L.L.Lu,T. Karnik, and V. K. De, “Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 49–63, Jan. 2009.
[5]D. Bull, S. Das, K. Shivashankar, G. S. Dasika, K. Flautner, and D.Blaauw, “A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 18–31, Jan. 2011.
[6]M. Fojtik, D. Fick, Y. Kim, N. Pinckney, D. Harris, D. Blaauw, and D. Sylvester, “Bubble Razor: An architecture-independent approach to timing-error detection and correction,” in IEEE ISSCC 2012 Dig.,Feb. 2012, pp. 488–490.
[7]Jinn-Shyan Wang; Keng-Jui Chang; Tay-Jyi Lin; Prasojo, R.W.; Chingwei Yeh, "A 0.36V, 33.3 µ W 18-band ANSI S1.11 1/3-octave filter bank for digital hearing aids in 40nm CMOS," VLSI Circuits (VLSIC), 2013 Symposium on , vol., no., pp.C254,C255, 12-14 June 2013
[8][2014][HotChip] Low-Power Fixed-Latency DSP Accelerator w/ Autonomous Minimum Energy Tracking
[9] O. Girard, “OpenMSP430 project”, available at opencore.org, Mar. 2010.
[10]MSP430x1xx Family User's Guide
[11] 王進賢, 潘昱夫, “TBLB和Dithered TBLB CMOS電路的可測性設計與分析”, 中正大學電機工程研究所
[12] 王進賢, 許耿彰, “以TBLB及Dithered TBLB技術設計低功耗MSP430之研究”, 中正大學電機工程研究所