臺灣博碩士論文加值系統

目錄
指導教授推薦書
口試委員會審定書
致謝 iii
摘要 iv
Abstract v
目錄 vii
圖目錄 ix
表目錄 xii
第一章緒論 1
1.1 發展背景 1
1.2 研究動機 2
1.3 論文組織 2
第二章文獻回顧 4
2.1 類比式工作週期校正電路 4
2.2 數位式工作週期校正電路 6
2.3 結論 15
第三章電路架構設計與實現 17
3.1 設計流程 19
3.2 電路架構簡介 20
3.3 內部電路架構介紹 24
3.3.1 半延遲線和粗調碼產生器 24
3.3.2 脈波產生器 29
3.3.3 細調偵測器 33
3.4 模擬結果 34
3.5 晶片佈局與規格表 40
3.6 結論 41
第四章晶片量測結果 42
4.1 晶片量測與環境設定 42
4.2 印刷電路板(Printed Circuit Board, PCB)設計 43
4.3 量測結果 46
4.4 電路設計規格 56
4.5 相關文獻之電路設計規格比較 58
第五章結論及未來研究方向 60
5.1 結論 60
5.2 未來研究方向 60
參考文獻 61

 
圖目錄
圖2.1類比式工作週期校正電路. 5
圖2.2 參考文獻[2] 之DCC 電路架構. 5
圖2.3參考文獻[2] 之延遲單元. 6
圖2.4 SMD型DCC. 7
圖2.5 (a) Phase-Alignment ADDCC (b) DLL部分的時序圖(c) DCC部分的時序圖 9
圖2.6 (a)Phase-Alignment ADDCC (b) DCC時序圖. 11
圖2.7 DCC電路架構圖. 12
圖2.8 Signal paths at (a) DCC phase and (b) deskew phase. 13
圖2.9 (a) ADDLL and ADDCC (b) ADDLL 時序圖 (c) ADDCC時序圖. 15
圖3.1時序圖. 18
圖3.2 設計流程. 19
圖3.3總電路架構圖. 20
圖3.4 時序圖. 21
圖3.5 (a) 量化架構圖 (b)Arbiter 25
圖3.6 (a)傳統2-1多工器 (b)新2-1多工器. 26
圖3.7 (a) 傳統多工器模擬 (a) 新多工器模擬. 27
圖3.8 (a) Half Delay Line架構圖 (b) 延遲線線性度圖. 28
圖3.9 (a)脈波產生器 (b)Clock Shaping (c) Fine Delay Line (d)SR latch (e) SR latch 模擬圖 31
圖3.10(a) Fine Delay Line線性圖(b)閘極-源極和閘極-汲極電容與VGS之關係圖. 32
圖3.11細調偵測器. 33
圖3.12模擬頻率1G，工作週期20%，Post-Simulation， (a)在TT情況下模擬結果，(b)在FF情況下模擬結果，(c)在SS情況下模擬結果. 35
圖3.13模擬頻率1G，工作週期80%，Post-Simulation， (a)在TT情況下模擬結果，(b)在FF情況下模擬結果，(c)在SS情況下模擬結果 36
圖3.14模擬頻率400M，工作週期20%，Post-Simulation， (a)在TT情況下模擬結果，(b)在FF情況下模擬結果，(c)在SS情況下模擬結果. 37
圖3.15模擬頻率400M，工作週期80%，Post-Simulation， (a)在TT情況下模擬結果，(b)在FF情況下模擬結果，(c)在SS情況下模擬結. 38
圖3.16 TT情況下工作週期誤差結果. 39
圖3.17 TT情況下相位誤差結果. 39
圖3.18晶片佈局圖. 40
圖4.1 量測晶片訊號輸出考量. 42
圖4.2 量測環境設備. 43
圖4.3印刷電路板上層. 44
圖4.4印刷電路板底層. 44
圖 4.5晶片腳位鎊線圖. 45
圖 4.6(a) 為實際印刷電路板上層圖形. 45
圖 4.6(b) 為實際印刷電路板下層圖形. 46
圖4.7 參考頻率 500MHz、工作週期20%量測. 47
圖4.8 參考頻率 500MHz、工作週期 50%量測. 48
圖4.9 參考頻率 500MHz、工作週期80%量測. 49
圖4.10 參考頻率 1000MHz、工作週期20%量測. 50
圖4.11 參考頻率 1000MHz、工作週期 50%量測. 51
圖4.12 參考頻率 1000MHz、工作週期 80%量測. 52
圖 4.12 參考頻率500MHz 相位抖動值量測. 53
圖 4.13 參考頻率 900MHz 相位抖動值量測. 54
圖4.14 工作週期誤差量測統計圖. 55
圖 4.15 相位誤差量測統計圖. 56
圖 4.16 峰對峰抖動與 RMS 抖動量測統計圖. 56
圖 4.17 整體晶片照片. 57
圖 4.18 核心晶片佈局照片. 58

表目錄
表3.1規格表. 40
表 4.1規格表. 56
表 4.2相關文獻比較表. 58

參考文獻(Reference)

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