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研究生:劉偉羿
研究生(外文):Wei-Yi Liou
論文名稱:高精確度及面積效益的固定長度布爾乘法器
論文名稱(外文):High-accuracy and Area-efficiency Fixed-width Booth Multiplier
指導教授:陳元賀
指導教授(外文):Yuan-Ho Chen
學位類別:碩士
校院名稱:中原大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:36
中文關鍵詞:固定長度乘法器超大型積體電路
外文關鍵詞:Booth MultipliersVLSI
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布爾乘法器(Booth Multiplier)廣泛的應用在各種超大型積體電路(VLSI)的設計中,然而乘法器是運算單元的主要元件,對架構的面積和運算速度有相當大的影響。因此,對布爾乘法器進行研究,提出面積更小,速度更快又滿足精確度要求的架構有很好的研究意義。 本研究開發了固定長度布爾乘法器的動態誤差補償電路的高精確度基於條件概率和計算機模擬。系統的解決方案基於條件概率和期望值的生成,利用計算機模擬和具有最高精確度的解決方案。所提出的方案除了是高精確度,也減少面積效益和提高功率效率。本研究中使用的TSMC 0.18-um CMOS製程的16位元布爾乘法器,運行速度達到100MHz和消耗功率為6.7mW。

Booth Multipliers are widely used in the design of various kinds of VLSI, while multiplier is the main component of arithmetic logic units(ALU), having a great effect on the area of architecture and instruction cycle.Therefore, it has a significant sense to make a research of the Booth multiplier and proposes an accurate architecture with lower area and higher speed.This paper developed a dynamic error-compensation circuit for fixed-width Booth multipliers of high accuracy based on probability and computer simulation . the proposed begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed approach is area-effective and power-efficient. This study used the TSMC 0.18-um CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.

目錄
第一章 簡介 1
第二章 固定長度布爾乘法器的架構及其概率特徵 8
2.1 固定長度布爾乘法器架構 8
2.2 固定長度布爾乘法器的概率特徵 14
第三章 誤差補償電路方法 7
3.1 基於概率方法的初步設計 17
3.2 基於模擬方案的最佳化設計 18
3.3 Proposed布爾乘法器 19
第四章 比較與晶片實作 21
第五章 總結 25
參考文獻 26

圖目錄
圖1.1 四進位乘法之運算規則 3
圖1.2 固定長度BOOTH乘法器的部分乘積架構圖 3
圖1.3 普通乘法器的部分乘積架構圖 4
圖1.4 固定長度BOOTH乘法器的四捨五入處理方法步驟一 4
圖1.5 固定長度BOOTH乘法器的四捨五入處理方法步驟二 4
圖1.6 固定長度BOOTH乘法器的直接捨去處理方法 6
圖1.7 文獻[21]中的核心選擇變數(KEY SELECT) 6
圖2.1 布爾編碼器(BOOTH ENCODER)的轉換流程圖 10
圖2.2 文獻[28]中的四捨五入模板 10
圖2.3 當ω = 1,2,3時的TP部分 11
圖2.4 8位元布爾乘法器當ω = 3時的TPmajor跟TPminor的劃分方法12
圖2.5 具有誤差補償電路的固定長度布爾乘法器的架構 13
圖3.1 列變數不同時的TP部分乘積 17
圖3.2 提出的8-BIT 補償電路 20
圖3.3 8-BIT乘法器的MP部分 20
圖4.1 論文的16位元乘法器佈局圖和電路特徵 25

表目錄
表2.1 BOOTH編碼器的轉換規則及其概率特徵 9
表2.2 部分乘積的生成機制 9
表2.1 Booth編碼器的轉換規則及其概率特徵 9
表2.2 部分乘積的生成機制 9
表2.3 部分乘積關於nzi的條件期望值 15
表2.4 部分乘積關於KVi的條件期望值 16
表4.1 初步設計的信噪比 23
表4.2 文獻方法對於面積和延遲對照表 23
表4.3 各文獻方法的信噪比 24





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