臺灣博碩士論文加值系統

本論文提出的寬操作範圍與低功率消耗的低頻率輸出數位控制振盪器應用於無線近身網路，設計的數位控制振盪器提供較佳的解析度，且能夠產生低頻率輸出訊號，與其它設計方式比較，能夠達到較低的功率消耗及電路低複雜度。
設計的數位控制振盪器使用兩級串接式架構，分別為粗調級與細調級，粗調級使用提出的史密特觸發交錯延遲細胞元件，串接數十個延遲細胞元件，達到寬操作範圍，細調級則使用基本邏輯閘，產生較小的延遲時間，有較高的延遲解析度。本論文提出的史密特觸發交錯延遲細胞元件，使用於提出的數位控制振盪器且應用於無線近身網路上，可以使用較小的面積，達到大的延遲時間與低功率消耗。此設計使用TSMC 0.18µm CMOS製程設計，操作頻率範圍為6.95~155.7MHz，延遲解析度為4.6ps，電路操作在6.96MHz時功率消耗為79.74µW。寬操作範圍、低功率消耗與高延遲解析度的數位控制振盪器適用於無線近身網路系統晶片上。
在系統晶片(System on Chip, SoC)中，使用本論文提出的數位控制振盪器應用於全數位鎖相迴路中的參考時脈，驗證電路的操作情形。電路使用基本邏輯閘與硬體描述語言去實現，可以減少設計上所需要的時間，以及降低電路的複雜度。

In this thesis, a wide range and a low power digitally controlled oscillator with low output frequency for wireless body area network (WBAN) are presented. The proposed digitally controlled oscillator not only can provide high resolution, but also can generate low frequency clock signal with low power consumption and low circuit complexity as compared with conventional approaches.
The proposed design digitally controlled oscillator employs a cascade-stage structure with coarse tuning and fine tuning. The coarse tuning uses the proposed Schmitt Trigger Interlaced to achieve wide range. The fine tuning uses delay cells to generate small delay to achieve high resolution. It can achieve long delay time and low power consumption with low cost. Simulation results show that the operation frequency range is from 6.95MHz to 155.7MHz, and the power consumption can be improved to 79.74µW (@6.96MHz) with 4.6ps resolution in TSMC 0.18µm CMOS process technology.
The proposed DCO is integrated into the ADPLL that used resulting of proposed DCO as reference clock to compare frequency with inner DCO to lock. The proposed design of ADPLL with some simple block that can use gate-level or Verilog Hardware Description Language (Verilog HDL) to implement. Thus, the design time and design complexity can be reduced by using Verilog HDL.

摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章　介紹 1
　　1.1　研究動機 1
　　1.2　論文組成 4
第二章　數位控制振盪器概要 6
　　2.1　時脈產生器之應用 6
　　2.2　數位控制振盪器之設計 6
　　　　2.2.1　汲取電流式架構 7
　　　　2.2.2　驅動能力調變式架構 7
　　　　2.2.3　延遲路徑選擇式架構 8
　　　　2.2.4　數位控制變容器架構 9
第三章　低頻率寬範圍數位控制振盪器 12
　　3.1　不同延遲細胞元件之分析 12
　　　　3.1.1　史密特觸發延遲元件 12
　　　　3.1.2　交錯延遲細胞元件 13
　　　　3.1.3　史密特觸發交錯延遲細胞元件 15
　　3.2　史密特觸發交錯延遲細胞元件特性 16
　　　　3.2.1　史密特觸發交錯延遲細胞元件之背景 16
　　　　3.2.2　史密特觸發交錯延遲細胞元件之傳輸延遲路徑 17
　　　　3.2.3　史密特觸發交錯延遲細胞元件之功率消耗 19
　　3.3數位控制振盪器架構 22
　　3.4子電路架構 23
　　　　3.4.1粗調級電路架構 23
　　　　3.4.2細調級電路架構 25
　　3.5模擬結果 26
　　　　3.5.1佈局前模擬(Pre-Simulation Layout) 26
　　　　3.5.2佈局後模擬(Post-Simulation Layout) 32
　　3.6總結 42
第四章　全數位鎖相迴路 43
　　4.1　簡介 43
　　4.2 全數位鎖相迴路之設計 44
　　　　4.2.1 相位頻率偵測器 45
　　　　4.2.2數位控制振盪器 47
　　　　4.2.3 數位控制器 49
　　4.2.4 除頻器 50
　　4.3 模擬結果 51
　　4.4 總結 53
第五章實作結果 54
　　5.1　設計流程 54
　　5.2　量測考量 56
　　5.3　量測結果 58
　　5.4　總結 62
第六章　結論與未來展望 63
參考文獻 64

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