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研究生:簡嘉韋
研究生(外文):Jia-Wei,Jian
論文名稱:應用於正子斷層掃瞄之高轉換速度與寬轉換範圍時間數位轉換器設計
論文名稱(外文):High-Conversion Rate and Wide-Range Time-to-Digital Converter for PET Applications
指導教授:盛鐸
指導教授(外文):Duo Sheng
口試委員:盛鐸黃執中林寬仁
口試委員(外文):Duo ShengChih-Chung HuangKuan-Jen Lin
口試日期:2015-06-30
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:49
中文關鍵詞:正子斷層掃瞄時間數位轉換器寬轉換範圍
外文關鍵詞:Positron Emission TomographyTime-to-Digital ConverterWide-Range
相關次數:
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本論文提出高轉換速度、寬轉換範圍且高解析度的時間數位轉換器,以cell-based做設計用於正子斷層掃描的應用上,此時間數位轉換器採取串接式的架構同時實現高解析度與寬轉換範圍。此外,根據設計的階層式串接架構,它不僅實現高速轉換,而且與傳統方法比起來有著低電路複雜度的優點。
  本論文提出兩個不同的時間數位轉換架構;第一種是以兩階層式串接的架構來達到高轉換速度與寬轉換範圍,在90nm的製程下,頻率為200 MHz時,解析度為50ps。另一種架構則是多階層式串接結合內插式架構來提高解析度,在0.18µm的製程下,為200MHz,解析度為約25ps。此外,由於電路可以standard cell來實現,使它有較佳的可攜性,能夠很容易的用於不同的製程,且非常適合用在正子斷層掃描的應用上。
In this thesis, high conversion rate, conversion wide range and high-resolution time-to-digital converter for positron emission tomography (PET) applications are presented. The proposed TDC not only can achieve high speed of operation, but also have low circuit complexity as compared with conventional approaches.
  This thesis presents two different time-to-digital architectures; the first proposed architecture employs a two-level cascade-stage structure to achieve high timing resolution and wide sampling range at the same time. Simulation results show that the proposed TDC can be improved to 200MHz with 50ps resolution in 90nm CMOS process technology. The second proposed architecture employs multi-level cascade-stage structure with interpolator to improve timing resolution, and achieve low power consumption, Simulation results show that the proposed TDC can be improved to 200MHz with 25ps resolution in 0.18µm CMOS process technology. In addition, the proposed TDC can be implemented with standard cells, making it easily portable to different processes and very suitable for biomedical chip applications.

摘要................................................................i
英文摘要...........................................................ii
誌謝..............................................................iii
目錄...............................................................iv
表目錄.............................................................v
圖目錄.............................................................vi
第一章 介紹........................................................1
1.1 研究動機...................................................1
1.2 論文組成...................................................8
第二章 時間數位轉換器介紹...........................................9
2.1 時間數位轉換器歷史介紹.....................................9
2.2 計數器方法................................................13
2.3 遲串列方法................................................13
2.4 游標尺延遲線方法..........................................15
2.5 游標尺振盪器方法..........................................16
2.6 兩階層快閃方法............................................17
2.7 時序放大器方法............................................18
2.7-1 SR栓鎖器方法.............................................19
2.7-2交錯耦合方法.............................................19
第三章 具高轉換速度與寬轉換範圍時間數位轉換器......................21
3.1 時間數位轉換器架構........................................21
3.2 時間數位轉換器電路模擬結果................................24
第四章 多階層高轉換速度時間數位轉換器設計..........................25
4.1 時間數位轉換器架構.........................................25
4.2 計數器式...................................................30
4.3 全數位延遲鎖定迴路架構.....................................31
4.3.1 數位控制器...............................................32
4.3.2 數位控制延遲線延遲元件架構...............................33
4.3.3 相位頻率偵測器...........................................35
4.4 延遲選擇電路架構...........................................36
4.5 內插式架構.................................................38
4.6 數位碼計算器...............................................41
第五章 實作方法...................................................42
5.1 設計流程...................................................42
5.2 晶片量測方法...............................................43
第六章 結論與未來展望..............................................45
參考文獻...........................................................46

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