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研究生:林俊宏
研究生(外文):Chun-Hung Lin
論文名稱:應用於快閃記憶體之分頁快取感知的寫入緩衝區管理方法
論文名稱(外文):A Page Cache-Aware Write Buffer Management Scheme for Flash-Based Storage Systems
指導教授:張軒彬張軒彬引用關係
口試委員:徐玉青曾秀松張大緯
口試日期:2015-07-31
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:38
中文關鍵詞:快閃記憶體寫入緩衝
外文關鍵詞:Nand Flash Memorywrite buffer
相關次數:
  • 被引用被引用:0
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  • 下載下載:10
  • 收藏至我的研究室書目清單書目收藏:0
固態硬碟使用快閃記憶體為其儲存媒介,具有體積小、質量輕、抗震性佳、耗電量低等優點,已被廣泛應用於行動裝置和嵌入式系統上。但因為Nand Flash Memory的物理特性為讀取與寫入速度不均、不能原地更新資料、寫入/抹除次數有限,所以對於寫入動作需要特別處理,否則會導致系統效能不佳。

而目前改善固態硬碟效能的方法是加入一塊write buffer,由於寫入緩衝的儲存媒介為RAM,對於經常被存取的熱門資料(hot data)就可以直接在write buffer更新資料,減少對快閃記憶體的寫入與抹除動作。此外,在主機端亦具有一分頁快取記憶體,傳統的分頁快取機制主要是當作硬碟的快取,當儲存裝置換成固態硬碟時,直接把舊的分頁快取機制套用在固態硬碟會犧牲其效率,因此有許多新研究的分頁快取演算法,將快閃記憶體的物理性質加入考量。

然而,目前分頁快取和寫入緩衝的方法主要還是獨自討論研究,本篇論文提出了Page Cache-Aware Write Buffer管理方法,希望透過跨階層合作的方式,藉由分享資訊,讓我們在write buffer做置換策略時可以做出準確的判斷,更加有效提升整體系統效能。


The storage medium of Solid State Drives (SSD) is NAND Flash Memory. It has many advantages such as small size, high shock resistance and low power. Due to these advantages, it has been widely used for mobile devices and embedded systems. However, due to certain physical characteristic of NAND Flash Memory, it has the asymmetric speed of read and write operations, inability to in-place updates, limited number of write and erase times. Consequently, we need to take proper operation for write operations; otherwise, it would lead to a degraded system performance.

To address the write issues of flash memory-based storage systems, one promising approach is to add a write buffer in SSDs. Since the storage medium of write buffer is RAM, hot data can in-place update in the write buffer to reduce frequent write and erase to flash memory. However, in the host computer systems, there is a memory-based page cache. The traditional replacement algorithms of page cache assumes that the secondary storage consists of hard disks. As a result, these replacement algorithm cannot be directly applied for SSDs. Hence, many new page cache management strategies for SSDs have been proposed in recent studies that consider the characteristics of Flash memory.

However, the current replacement algorithms on page cache and write buffer are designed separately. To address this issue, in this thesis, we propose a page cache-aware write buffer management scheme. By the idea of cross-layer design, the page cache can pass information to the write buffer. Then, by this information, the write buffer replacement policy can select a more suitable victim for replacement, so as to optimize the performance of the SSDs.



第一章 緒論 1
1.1 簡介 1
1.2 研究動機 2
1.3 貢獻 3
1.4 論文架構 3
第二章 背景知識與相關研究 4
2.1 NAND Flash Memory 4
2.2  Flash Translation Layer 5
2.2.1 Address Mapping 6
2.2.2 Garbage Collection 9
2.2.3 Wear Leveling 9
2.3 Page Cache 9
2.3.1 CFLRU 9
2.3.2 LRU-WSR 10
2.3.3 AD-LRU 11
2.4 Write Buffer 12
2.4.1 FAB 12
2.4.2 BPLRU 13
2.4.3 CLC 15
2.4.4 BPAC 16
第三章 Page Cache-Aware Write buffer Management Scheme 18
3.1 系統架構 18
3.2 Problem Definition 19
3.3 Page-Cache-Aware Write Buffer Management 21
3.4 Write Buffer Memory Management 23
3.5 運作流程 25
第四章 實驗結果與討論 27
4.1 實驗環境 27
4.2 實驗結果 28
第五章 結論及未來工作 34
參考文獻 35
附錄 38
1. DiskSim安裝流程 38
2. 遇到的問題 38


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[2] H. Kim and S. Ahn, “BPLRU: A buffer management scheme for
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