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研究生:鄭吉峰
研究生(外文):Ji-Feng Zheng
論文名稱:針對時脈延遲錯誤的靜態壓密之研究
論文名稱(外文):Static Compaction Algorithm for Clock Delay Faults
指導教授:王行健
口試委員:李淑敏鄭經華
口試日期:2015-07-27
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:45
中文關鍵詞:壓密電路
外文關鍵詞:compactioncircuit
相關次數:
  • 被引用被引用:0
  • 點閱點閱:49
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  • 下載下載:4
  • 收藏至我的研究室書目清單書目收藏:0
在數位系統中,時脈訊號(Clock Signals)的使用無所不在,但若在測試的過程中產生時脈歪斜(Clock Skew),將造成電路無法正確執行,所以對於時脈延遲(Clock Delay)的測試是需要的。雖然可藉由測試正反器(Flip-Flop)到正反器的最長路徑是否因時脈延遲影響產生錯誤,來降低測試複雜度,但對較大的電路而言,測試資料還是過於龐大。
本篇論文提出對時脈延遲的測試向量進行靜態壓密,並使用六種不同的方法進行壓密,分別比較壓密後的結果,其中又有對不同來源之路徑的測試向量進行壓密比較,觀察對路徑進行壓密的方法是否比一般壓密的效果還好。
本論文使用ISCAS’89的實驗電路進行實驗,雖然在最長路徑方面傳統壓密的效率較高,但若在不同來源之路徑方面,對路徑壓密的方法與傳統壓密方法的壓密率相當接近。


致謝 i
摘要 ii
目錄 iii
表目錄 iv
圖目錄 v
第一章 簡介 1
1.1. 研究動機與目標 1
1.2 內容大綱 3
第二章 背景知識與相關研究 4
2.1. 錯誤路徑(False Path) 4
2.2. PODEM 5
2.3. 靜態壓密(Static Compaction) 6
2.4. 延遲錯誤(Delay Fault) 7
2.5. 路徑延遲錯誤模型(Path Delay Fault Model) 9
第三章 問題描述與實作流程 13
3.1. 問題描述 13
3.2. 排除錯誤路徑 17
3.3. 測試向量壓密 18
3.4. 壓密後模擬 23
3.5. 找尋新路徑 26
3.6. 實作流程 27
第四章 實驗結果與分析 28
4.1. 最長路徑 29
4.2. 不同來源之路徑 36
4.3. 找尋新路徑 41
第五章 結論 42
參考文獻 43


參考文獻
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