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研究生:游汶艗
研究生(外文):Wen-Yi Yu
論文名稱:基於統計式靜態時序分析的時脈偏移偵測方法
論文名稱(外文):Clock Skew Detection Based on Statistical Static Timing Analysis
指導教授:王行健
口試委員:李淑敏鄭經華
口試日期:2015-07-27
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:39
中文關鍵詞:時脈偏移關鍵路徑
外文關鍵詞:clock skewCritical Path
相關次數:
  • 被引用被引用:0
  • 點閱點閱:77
  • 評分評分:
  • 下載下載:9
  • 收藏至我的研究室書目清單書目收藏:0
受先進製程技術進步的影響,製程漂移 (Process Variation) 產生的時脈偏移 (Clock Skew) 對時序驗證 (Timing Verification) 及時脈樹合成 (Clock Tree Synthesis, CTS ) 形成巨大的挑戰。
過去在同步數位電路的研究中,主要關注於測試組合邏輯 (Combinational Logic) 上的延遲錯誤 (Delay Fault) ,較少針對測試時脈延遲錯誤 (Clock Delay Faults) 做系統性的分析,本篇論文使用統計式靜態時序分析,提供一個有效的方法找出同步電路中,各正反器間可能發生時脈偏移的關鍵路徑,並加入錯誤路徑的分析,使分析的結果貼近真實電路的情形。


致謝 i
摘要 ii
目錄 iii
圖目錄 iv
表目錄 v
第一章、簡介 1
1.1. 研究動機與目標 1
1.2. 內容大綱 2
第二章、背景知識與相關研究 3
2.1. 製程漂移 (Process Variation) 3
2.2. 同步時序電路 (Synchronous Sequential Circuits) 的時間分析 5
2.3. 靜態時序分析 (Static Timing Analysis, STA) 10
2.4. 統計式靜態時序分析 (Statistical Static Timing Analysis, SSTA) 11
2.5. 錯誤路徑 (False Path) 14
2.6. 時脈分佈網路 (Clock Distribution Network, CDN) 15
第三章、問題描述與定義 18
3.1. 問題描述 18
3.2. 問題定義 22
第四章、方法與實作 24
4.1. 基本運算 24
4.2. 參數設定 26
4.3. 計算關鍵率 27
4.4. 檢查錯誤路徑 28
4.5. 演算法與流程圖 29
第五章、實驗結果與分析 31
第六章、結論 35
參考文獻 36



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