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研究生:廖少祺
研究生(外文):Shao-Chi Liao
論文名稱:預先編碼Radix-4布斯乘法器
論文名稱(外文):Pre-encoded Radix-4 Booth Multiplier
指導教授:張延任
指導教授(外文):Yen-Jen Chang
口試委員:阮聖彰蔡坤霖張孟洲
口試委員(外文):Shanq-Jang RuanKun-Lin TsaiMeng-Chou Chang
口試日期:2015-07-16
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:72
中文關鍵詞:布斯乘法器布斯編碼Radix-4 布斯演算法改良式布斯平行運算乘法器
外文關鍵詞:Booth multiplierBooth encodingRadix-4 BoothModified Booth multiplierparallel multiplier
相關次數:
  • 被引用被引用:0
  • 點閱點閱:238
  • 評分評分:
  • 下載下載:19
  • 收藏至我的研究室書目清單書目收藏:0
乘法運算在許多應用之中被廣泛使用,因此乘法器的功率消耗是一個重要的議題。在本篇論文中,我們提出一種新式的改良式布斯編碼(MBE),並透過預先編碼器實現低功率消耗的布斯乘法器。我們的設計在編碼0倍時會將布斯解碼器關閉,避免解碼器在這個情況中不必要的運算,並強制將輸出設定為0。與先前的研究相比,我們的設計在8位元的乘法中,一列編解碼器的動態功率消耗節省約25%,所使用的電晶體數量節省約10%。在16位元的乘法中,一列編解碼的動態功率消耗節省約34%,所使用的電晶體數量節省約12%。在效能與靜態功率消耗也優於先前的研究。

Multiplication is widely used in many applications, thus, the power consumption of the multiplier is important issue. In this paper, we propose a new modified Booth encoding (MBE) scheme with a pre-encoder to improve the power consumption of the multiplier. This pre-encoder will disable the booth decoders which are unnecessary to be active in the 0X case, and set the outputs of decoders to 0. Compared with the previous approach, our design reduces 25% dynamic power consumption and 10% the transistor count of booth encoder and decoder for an 8-bit multiplication. For a 16-bit multiplication, our design reduces 34% dynamic power consumption and 12% transistor count. The performace and static power consumption are also better than previous studies.

目錄
中文摘要 i
英文摘要 iii
目錄 v
表格目錄 vi
圖目錄 viii
1、 簡介 1
2、 乘法器(Multiplier) 3
2.1. 陣列式乘法器 6
2.2. Radix-2 布斯乘法器 10
2.3. Radix-4 布斯乘法器 13
2.4. 相關研究 19
3、 預先編碼Radix-4布斯乘法器設計 29
3.1. 設計動機 29
3.2. 解碼器設計 31
3.3. 編碼器設計 37
3.4. 預先編碼器的電路設計 40
3.5. 與參考文獻[8]比較 47
4、 實驗結果分析 49
4.1. 模擬時序分析 49
4.2. 功率消耗分析 54
4.3. 延遲時間與電晶體數量分析 60
4.4. 乘法器整體平均功率消耗分析 62
4.5. 相關應用分析 64
5、 結論 69
6、 未來展望 70
7、 參考文獻 71



[1] S.-R. Kuang, J.-P. Wang and C.-Y. Guo, “Modified Booth multipliers with a regular partial product array,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 56, no. 5, pp. 404–408, May 2009.

[2] A. D. Booth, “A Signed Binary Multiplication Technique”, The Quaterly Journal of Mechanics and Applied Mathematics, vol.4, p. 236-240, Aug. 1951.

[3] O. L. Macsorley, “High-Speed Arithmetic in Binary Computers,” Proceedings of the IRE, vol.49, no.1, pp. 67-91, Jan. 1961.

[4] M. D. Ercegovac and T. Lang, Digital Arithmetic, Morgan Kaufmann Publishers, Los Altos, CA 94022, USA, 2003.

[5] I. S. Abu-Khater, A. Bellaouar and M. I. Elmasry, “Circuit techniques for CMOS low-power high-performance multipliers,” IEEE Journal of Solid-State Circuits, vol. 31, no. 10, pp.1535-1546, Oct. 1996.

[6] R. Fried, “Minimizing energy dissipation in high-speed multipliers,” International Symposium on Low Power Electronics and Design (LPE), Aug. 1997, pp. 214-219.

[7] W.-C. Yeh and C.-W. Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, vol. 49, no. 7, pp. 692-701, Jul. 2000.

[8] Z. Huang and M. D. Ercegovac, “High-Performance Low-Power Left-to-Right Array Multiplier Design,” IEEE Transactions on Computers, vol. 54, no. 3, pp. 272-283, Mar. 2005.

[9] N. Ohkubo et al., “A 4.4 nS CMOS 54 x 54-b Multiplier Using Pass-Transistor Multiplexer”, IEEE Journal of Solid-State Circuits, vol. 30, no. 3, pp. 251-257, Mar. 1995.

[10] G. Goto et al., “A 54 x 54-b Regularly Structured Tree Multiplier”, IEEE Journal of Solid-State Circuits, vol. 27, no. 9, pp. 1229-1235, Sep. 1992.

[11] Z. Huang, “High-Level Optimization Techniques for Low-Power Multiplier Design,” PhD dissertation, Univ. of California, Los Angeles, June 2003.

[12] National Chip Implementation Center [Online], Available: http://www.cic.org.tw

[13] L.-D. Van, S.-S. Wang, and W.-S. Feng, “Design of the lower-error fixedwidth multiplier and its application,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 1112–1118, Oct. 2000.

[14] C.-Y. Li, Y.-H. Chen, T.-Y. Chang, and J.-N. Chen, “A probabilistic estimation bias circuit for fixed-width Booth multiplier and its DCT applications,” IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 58, no. 4, pp. 215–219, Apr. 2011.

[15] J.-Y. Kang and J.-L. Gaudiot, “A Fast and Well-Structured Multiplier,” Euromicro Symposium on Digital System Design, Sep. 2004, pp. 508-515.

[16] D. Villeger and V. G. Oklobdzija, “Analysis of booth encoding efficiency in parallel multipliers using compressors for reduction of partial products,” Conference on Signal, Systems and Computers, Nov. 1993, pp. 781–784.

[17] J. Park, S. Kim and Y.-S. Lee, “A Low-Power Booth Multiplier Using Novel Data Partition Method,” Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (APASIC), Aug. 2004, pp. 54-57.

[18] S. Nishizawa, T. Ishihara, and H. Onodera, “Analysis and comparison of XOR cell structures for low voltage circuit design,” International Symposium on Quality Electronic Design (ISQED), Mar. 2013, pp. 703-708.

[19] S.-R. Kuang and J.-P. Wang, “Design of Power-Efficient Configurable Booth Multiplier,” IEEE Transactions on Circuits and Systems I: Regular Papers, Mar. 2010, pp. 568-580.


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