在高介電常數世代，二氧化鉿是一個取代二氧化矽最佳的選擇，然而卻會使n型金氧半場效電晶體產生嚴重的陷阱捕捉效應，進而導致可靠度問題，加入二氧化鋯能改善二氧化鉿的電性與可靠度。另一方面，在奈米級電晶體中過量的低頻雜訊(包含1/f雜訊與隨機擾動雜訊)會限制類比、數位、混訊與射頻等線路功能。然而，針對二氧化鉿摻伴二氧化鋯的介電層閘極堆疊，過去的研究只是侷限在元件性能、電容電壓遲滯與可靠度等特性。本論文是藉由1/f、隨機擾動雜訊與電容電壓遲滯的量測來調查二氧化鉿、二氧化鋯與鉿鋯複合二氧化物的陷阱特性。所以，本論文的成果可以擴展過去研究的領域。
從n型金氧半場效電晶體的研究中發現，元件中有二氧化鉿或鉿鋯複合二氧化物薄膜的1/f雜訊機構歸類於載子數擾動，故能顯現出較高的氧化物陷阱密度。而且，陷阱捕捉的行為主要是由二氧化鉿薄膜主導。而在二氧化鋯/二氧化鉿/二氧化矽的閘極堆疊中，陷阱捕捉的表現是取決於初層二氧化鉿之厚度。另外，具有純二氧化鋯閘極介電層之參照元件的1/f雜訊機構則一致於包含載子數擾動及關連載子遷移率擾動的統合模型。
再則，從p型金氧半場效電晶體的研究中發現，所有的測試元件包含二氧化鉿、二氧化鋯與鉿鋯複合二氧化物薄膜的1/f雜訊機構都屬於統合模型。隨機擾動雜訊的結果呈現出二氧化鋯元件是在所有測試元件中具有最深的陷阱深度，如此表示：二氧化鋯高介電常數閘極堆疊擁有最深的有效固定電荷中心。因此，二氧化鋯元件顯示出最高的氧化物陷阱密度，透由摻伴二氧化鉿薄膜可以達到抑制因二氧化鋯造成的電洞捕捉之陷阱行為。
比較所有n及p型金氧半場效電晶體的特性結果發現：電容電壓遲滯大小與氧化物陷阱密度高低趨勢一致，故電容電壓遲滯的量測可作為氧化物陷阱特性的定性研究。另外，藉由推導得出之氧化物陷阱密度的主要源頭是邊緣陷阱，這是靠近二氧化矽與矽基底之界面的陷阱。檢視分子軌域圖，二氧化鉿材料顯露出較多的靠近導帶之氧空隙缺陷，所以容易造成電子捕捉。反之，二氧化鋯材料展現出較多的靠近價帶之氧插入缺陷，所以容易造成電洞捕捉。
最後，從源極/汲極嵌入矽鍺之p型金氧半場效電晶體的研究發現：元件通道中的單軸壓縮應變會導致穿隧衰退係數減小而反應在氧化物陷阱深度。必然地，由於較少的載子擾動，較低的1/f 雜訊就會被觀察到，這樣的結果顯現出源極/汲極嵌入矽鍺之p型金氧半場效電晶體對低頻雜訊特性具有本質上的好處。

In high-k (HK) generation, HfO2-based gate dielectrics, which are the best choice for replacing SiO2, cause serious trapping effects in nMOSFETs, resulting in some reliability issues. Adding ZrO2 can improve the electrical and reliability properties of HfO2-based oxides. On the other hand, excessive low-frequency noise, which includes 1/f noise and random telegraph noise (RTN), in nanoscale transistors leads to a limitation in the functionality for analog, digital, mixed-signal, and RF circuits. However, previous studies have only reported the device performance, C-V hysteresis, and reliability properties of devices with ZrO2-added HfO2 dielectric gate stacks. This dissertation work investigated trap properties of HfO2, ZrO2 and composited HfxZr1-xO2 gate dielectrics in 28-nm n- and p-MOSFETs by 1/f, RTN and C-V hysteresis measurements, which can expand fields of past researches.
For nMOSFETs, the mechanism of 1/f noise in device with HfO2 or HfxZr1-xO2 films was described by carrier number fluctuation, showing higher oxide trap densities (Nt). Furthermore, it was found that the trapping behavior was mainly dominated by the HfO2 film and was dependent on the thickness of the initial HfO2 layer in the ZrO2/HfO2/SiO2 gate-stack. Besides, reference devices with a pure ZrO2 gate dielectric exhibited 1/f noise characteristics that are consistent with the unified model, which incorporates both the carrier number and the correlated mobility fluctuations.
For pMOSFETs, the mechanism of 1/f noise in all tested devices with HfO2, Hf0.83Zr0.17O2, and ZrO2 films was described by the unified model. RTN results demonstrated that ZrO2 device had the deepest trap depth (xT) among all devices, indicating that ZrO2 HK gate stacks had a deepest effective centroid of the fixed charges. As a result, the device with ZrO2 exhibited the highest Nt value. Fortunately, the trapping behavior of hole capture from a ZrO2 film can be suppressed through mixing with a HfO2 film.
Comparing the trap properties of all tested n- and p-MOSFETs, it was found that the trend of C-V hysteresis was consistent with that of Nt value. So, C-V hysteresis measurement can be a qualitative method for the estimation of trap properties. Further, the source of the extracted Nt was mainly from border traps which are the traps near the interface of SiO2 interfacial layer and Si substrate. From molecular orbital diagrams, HfO2 material exhibits more oxygen vacancy defects near conduction band to cause electron trapped easily. In contrast, ZrO2 material reveals more oxygen interstitial defects near valence band to make hole trapped easily.
Finally, for pMOSFETs with embedded SiGe source/drain, the uniaxial compressive strain in the device channel induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth. Consequently, lower 1/f noise

Chinese Abstract I
English Abstract III
Acknowledgement V
Contents VI
Figure Captions IX
Table Captions XIV

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation and Objective 3
1.3 Dissertation Organization 4
Reference 6
Chapter 2 Process, Theory and Method 16
2.1 Process 16
2.1.1 HKMG Gate Stacks Process Flow 16
2.1.2 ALD Process for HK Gate Dielectric Deposition 17
2.1.3 HfO2 Is Prevalent for CMOS Applications 18
2.1.4 Uniaxial Compressive Stress 19
2.1.4.1 Physics of Strain Effects in CMOS Transistors 19
2.1.4.2 Strained-Si pMOSFET Device 20
2.2 Theory and Method 21
2.2.1 HK Gate Dielectric Characterization by C-V 21
2.2.2 1/f Noise and Noise in MOSFETs 22
2.2.2.1 1/f Noise 22
2.2.2.2 Noise in MOSFETs 24
2.2.2.2.1 S/D Noise in MOSFETs 24
2.2.2.2.2 1/f noise in MOSFETs 24
2.2.3 Border Traps 27
2.2.3.1 Border Traps Theory 28
2.2.3.2 Border Traps Measurement 29
2.2.3.2.1 C-V Hysteresis 30
2.2.3.2.2 Oxide Trapped Density (Nt) Extracted by 1/f Measurements 31
2.2.3.2.3 Trap Depth Extracted by RTN Measurements 31
Reference 34
Chapter 3 Low-Frequency Noise Characteristics for Various ZrO2-added HfO2-based 28 nm High-k/Metal-gate nMOSFETs 61
3.1 Introduction 61
3.2 Devices 62
3.3 Result and Discussion 63
3.4 Conclusion 65
Reference 67
Chapter 4 Investigation of Trap Properties of Hf0.83Zr0.17O2 High-k Gate Stack pMOSFETs by Low-frequency (1/f ) Noise and RTN Analyses 80
4.1 Introduction 80
4.2 Experiment 81
4.3 Results and Discussion 82
4.4 Conclusion 85
Reference 86
Chapter 5 Trap Properties of HfO2, Hf0.83Zr0.17O2 and ZrO2 High-k Gate Stacks in n- and p-MOSFETs 103
5.1 Introduction 103
5.2 Experiment 104
5.3 Results and Discussion 105
5.4 Conclusion 106
Reference 108
Chapter 6 Investigation of Low-Frequency Noise Characterization of 28-nm High-k pMOSFETs with Embedded SiGe Source/Drain 116
6.1 Introduction 116
6.2 Experiment 118
6.3 Results and Discussion 118
6.4 Conclusion 122
Reference 123
Chapter 7 Conclusion and Future Works 138
7.1 Conclusion 138
7.2 Suggested Future Works 140
Reference 141
Appendix A: Author Resume 142
Appendix B: Publication List 143

Chapter 1
[1.1]G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advanced gate dielectrics, J. Appl. Phys., 87, 484, 2000.
[1.2]Chris Auth, Mark Buehler, Annalisa Cappellani, Chi-hing Choi, Gary Ding, Weimin Han, Subhash Joshi, Brian McIntyre, Matt Prince, Pushkar Ranade, Justin Sandford, and Christopher Thomas, “45nm High-k+Metal Gate Strain-Enhanced Transistors, Intel Technology Journal, Volume 12, Issue 2, pp. 77-85, 2008
[1.3]IEDM 2010 Short Course: Reliability
[1.4]C. Leroux, J. Mitard, and F. Martin, “Characterization and Modeling of Hysteresis Phenomena in High-k Dielectrics, IEDM Tech. Dig., 2004, pp. 734-740.
[1.5]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, R. Gregory, X.-D. Wang, M. Canonico, D. Roan, E. A. Hebert, K. Kim, J. Jiang, R. Rai, V. Kaushik, S. B. Samavedam, and N. Rochat, “Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics, J. Vac. Sci. Technol., vol. B 25, no. 3, pp. 845-852, 2007.
[1.6]R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S. A. Sahhaf, and G. Groeseneken, “Review of Reliability Issue in High-k/Metal Gate Stacks, IPFA 15th International Symposium, 2008, pp. 1-6.
[1.7]S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantummechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide in nMOSFET’s, IEEE Electron Device Lett., vol. 18, issue 5, pp. 209-211, May 1997.
[1.8]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors, Rep. Prog. Phys. 69, pp. 327–396, 2006.
[1.9]G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations, J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[1.10]K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with Si, J. Mater. Res., issue 11, 2757-2776, 1996.
[1.11]J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices, J. Vac. Sci. Technol., B18, 1785, 2000.
[1.12]Gusev, E. P., Buchanan, D. A., Cartier, E., Kumar, A., DiMaria, D., Guha, S., Callegari, A., Zafar, S., Jamison, P. C., Neumayer, D. A., Copel, M., Gribelyuk, M. A., Okorn-Schmidt, H., D'Emic, C., Kozlowski, P., Chan, K., Bojarczuk, N., Ragnarsson, L.-A., Ronsheim, P., Rim, K., Fleming, R. J., Mocuta, A., and Ajmera, A., “Ultrathin high-K gate stacks for advanced CMOS devices, IEDM Tech. Dig., 2001, 455.
[1.13]Hegde, R. I., Triyoso, D. H., Tobin, P. J., Kalpat, S., Ramon, M. E., Tseng, H.-H., Schaeffer, J. K., Luckowski, E., Taylor, W. J., Capasso, C. C., Gilmer, D.C., Moosa, M., Haggag, A., Raymond, M., Roan, D., Nguyen, J., La, L. B., Hebert, E., Cotton, R., Wang, X.-D., Zollner, S., Gregory, R., Werho, D., Rai, R. S., Fonseca, L., Stoker, M., Tracy, C., Chan, B. W., Chiu, Y. H., and White, B. E., Jr., “Microstructure Modified HfO2 Using Zr Addition with TaxCy Gate for Improved Device Performance and Reliability, IEDM Tech. Dig., 2005, pp. 35-38.
[1.14]Hyung-Suk Jung, So-Ah Lee, Sang-ho Rha, Sang Young Lee, Hyo Kyeom Kim, Do Hyun Kim, Kyu Hwan Oh, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, Nae-In Lee, and Cheol Seong Hwang, “Impacts of Zr Composition in Hf1−xZrxOy Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 2094-2103, 2011.
[1.15]Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors for analog applications, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 921-927, 2001.
[1.16]B. Razavi, “A study of phase noise in CMOS oscillators, IEEE J. Solid-State Circuits, vol. 31, issue 3, pp. 331-343, 1996.
[1.17]M. J. Deen and O. Marinov, “Noise in advanced electronic devices and circuits, in Proc. Int. Conf. Noise and Fluctuations (ICNF), 2005, pp. 3-12.
[1.18]ITRS roadmap, 2005 edition (see http://www.itrs.net)
[1.19]Lucovsky, G., “Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity, J. Vac. Sci. Technol., A19, 1553, 2001.
[1.20]J. Robertson, “Interfaces and defects of high-K oxides on silicon, Solid-State Electron., 49, issue 3, 283-293, 2005.
[1.21]Westlinder, J., Schram, T., Pantisano, L., Cartier, E., Kerber, A., Lujan, G. S., Olsson, J., and Groeseneken, G., “On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices, IEEE Electron Device Letters, vol. 24, issue 9, 87, 2003.
[1.22]G Bersuker, P Zeitzoff, and G Brown, H. R. Huff, “Dielectrics for future transistors, Mater. Today, vol. 7, issue 1, 26-33, 2004.
[1.23]L. Pantisano, E. Cartier, A. Kerber, R. Degraeve1, M. Lorenzini, M. Rosmeulen, G. Groeseneken, and H. E. Maes, “Dynamics of threshold voltage instability in stacked high-K dielectrics: role of the interfacial oxide, VLSI Tech. Dig., 2003, 163.
[1.24]
Zafar, S., Callegari, A., Gusev, Evgeni, and Fischetti, M. V., “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks, J. Appl. Phys., vol.93, issue 11, 9298-9303, 2003.
[1.25]
J. R. Hauser and K. Ahmed, “Characterization of Ultrathin Oxides Using Electrical C-¬V and I-V Measurements, presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[1.26]Rashmi Jha, Gurganos, J., Kim, Y. H., Choi, R., Lee, Jack, and Misra, V., “A Capacitance-Based Methodology for Work Function Extraction of Metals on High-K, IEEE Electron Device Letters, vol. 25, issue 6, June 2004.
[1.27]Fleetwood, D. M., “Border traps in MOS devices, IEEE Trans. Nucl. Sci. 39, issue 2, 269-271, 1992.
[1.28]D. M. Fleetwood, P. S. Winokur, R. A. Reber Jr., T. L. Meisenheimer, J. R. Schwank, M. R. Shaneyfelt, and L. C. Riewe, “Effects of oxide traps, interface traps, and border traps on MOS devices, J. Appl. Phys. 73, 5058, 1993.
[1.29]Fleetwood, D. M., “Fast and slow border traps in MOS devices, IEEE Trans. Nucl. Sci. 43, 779, 1996.

Chapter 2
[2.1]C. K. Chiang Dr. Thesis: Institute of Microelectronics and Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, 2007.
[2.2]C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, “45nm High-k + Metal Gate Strain-Enhanced Transistors, VLSI Tech. Dig., 2008, pp. 128-129.
[2.3]L.-Å. Ragnarsson, Z. Li, J. Tseng, T. Schram, E. Rohr, M. J. Cho, T. Kauerauf, T. Conard, Y. Okuno, B. Parvais, P. Absil, S. Biesemans, and T. Y. Hoffmann, “Ultralow-EOT (5 Å) Gate-First and Gate-Last High Performance CMOS Achieved by Gate-Electrode Optimization, IEDM Tech. Dig., 2009, pp. 663-666.
[2.4]F. Arnaud, J. Liu, Y. M.Lee, K. Y.Lim, S. Kohler, J. Chen, B. K. Moon, C. W. Lai, M. Lipinski, L. Sang, F. Guarin, C. Hobbs, P. Ferreira, K. Ohuchi, J. Li, H. Zhuang, P. Mora, Q. Zhang, D. R. Nair, D. H. Lee, K. K. Chan, S. Satadru, S. Yang, J. Koshy, W. Hayter, M. Zaleski, D. V. Coolbaugh, H. W. Kim, Y. C. Ee, J. Sudijono, A. Thean, M. Sherony, S. Samavedam, M. Khare, C. Goldberg, and A. Steegen, “32nm General Purpose Bulk CMOS Technology for High Performance Applications at Low Voltage, IEDM Tech. Dig., pp. 633-636, 2008.
[2.5]T. Tomimatsu, Y. Goto, H. Kato, M. Amma, M. Igarashi, Y. Kusakabe, M. Takeuchi, S. Ohbayashi, S. Sakashita, T. Kawahara, M. Mizutani, M. Inoue, M. Sawada, Y. Kawasaki, S. Yamanari, Y. Miyagawa, Y. Takeshima, Y. Yamamoto, S. Endo, T. Hayashi, Y. Nishida, K. Horita, T. Yamashita, H. Oda, K. Tsukamoto, Y. Inoue, H. Fujimoto, Y. Sato, K. Yamashita, R. Mitsuhashi, S. Matsuyama, Y. Moriyama, K. Nakanishi, T. Noda, Y. Sahara, N. Koike, J. Hirase, T. Yamada, H. Ogawa, and M. Ogura, “Cost-effective 28nm LSTP CMOS Using Gate-First Metal Gate/High-k Technology, VLSI Tech. Dig., pp. 36-37, 2009.
[2.6]H. R. Harris, P. Kalra, P. Majhi, M. Hussain, D. Kelly, J. Oh, D. He, C. Smith, J. Barnett, P. D. Kirsch, G. Gebara, J. Jur, D. Lichtenwalner, A. Lubow, T. P. Ma, G. Sung, S. Thompson, B. H. Lee, H.-H. Tseng, and R. Jammy, “Band-engineered Low PMOS VT with High-k/Metal Gates Featured in a Dual Channel CMOS Integration Scheme, VLSI Tech. Dig., pp. 154-155, 2007.
[2.7]K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks , R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, IEDM Tech. Dig., 2007, pp. 247–250.
[2.8]K. Choi, H. Jagannathan, C. Choi, L. Edge, T. Ando, M. Frank, P. Jamison, M. Wang, E. Cartier, S. Zafar, J. Bruley, A. Kerber, B. Linder, A. Callegari, Q. Yang, S. Brown, J. Stathis, J. Iacoponi, V. Paruchuri, and V. Narayanan, “Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond, VLSI Tech. Dig., pp. 138-139, 2009.
[2.9]D. Riihela, M. Ritala, R. Matero, and M. Leskela, “Introducing atomic layer epitaxy for the deposition of optical thin films, Thin Solid Films, vol. 289, issue 1-2, pp. 250-255, 1996.
[2.10]E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, and M. Copel., AVS Topical Conf. on Atomic Layer Deposition, May 14, 2001.
[2.11]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors, Rep. Prog. Phys. 69, pp. 327–396,2006.
[2.12]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, R. Gregory, X.-D. Wang, M. Canonico, D. Roan, E. A. Hebert, K. Kim, J. Jiang, R. Rai, V. Kaushik, S. B. Samavedam, and N. Rochat, “Characteristics of atomic-layer-deposited thin HfZrO2 gate dielectrics, J. Vac. Sci. Technol. B, vol. 25, no. 3, pp. 845-852, 2007.
[2.13]Hyung-Suk Jung, So-Ah Lee, Sang-Ho Rha, S. Y. Lee, H. K Kim, Do Hyun Kim, Kyu Hwan Oh, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, Nae-In Lee, and Cheol Seong Hwang, “Impacts of Zr Composition in Hf1−xZrxOy Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics, IEEE Trans. Electron Devices, Vol. 58, No. 7, pp. 2094-2103, 2011.
[2.14]C. K. Chiang, Chang, J. C., Liu, W. H., Liu, C. C., Lin, J. F., Yang, C. L., Wu, J. Y., Chiang, C. K., and Wang, S. J., “A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric, Reliability Physics Symposium (IRPS), 2012, pp. GD.3.1 - GD.3.4
[2.15]P. Srinivasan Dr. Thesis: CHARACTERIZATION AND MODELING OF LOW-FREQUENCY NOISE, NJIT, USA, 2007.
[2.16]Shih-Chang Chen Dr. Thesis: A Study of Electrical Characteristics and Reliability in CMOSFETs with High-κ Gate Dielectrics, NCTU, ROC, 2009.
[2.17]G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties consideration, J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[2.18]P. Srinivasan, E. Simoen, and D. Misra, “Low-Frequency (1/f) Noise Performance of n- and p-MOSFETs with Poly-Si/Hf-Based Gate Dielectrics, J. Electrochem. Soc., Vol. 153, No. 4, pp. G324-G329, 2006.
[2.19]P. Magnone, C. Pace, F. Crupi, and G. Giusi, “Low Frequency Noise in nMOSFETs with Subnanometer EOT Hafnium-Based Gate Dielectrics, Microelectronics Reliability, Vol. 47, No. 12, pp. 2109-2113, 2007.
[2.20]W. H. Wu, B. Y. Tsui, M. C. Chen, Yong-Tian Hou, Yin Jin, Hun-Jan Tao, Shih-Chang Chen and M. S. Liang, “Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High-κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method, IEEE Trans. Electron Devices, Vol. 54, No. 6, pp. 1330-1337, 2007.
[2.21]M. Rafik, X.Garros, and C.Ouvrard, “Impact of TiN Metal Gate on NBTI Assessed by Interface States and Fast Transient Effect Characterization, IEDM Tech. Dig., 2007, pp. 825-828.
[2.22]G. Ribes, M. Rafik, and D. Roy, “Reliability Issues for Nano-Scale CMOS Dielectrics, Microelectronic Engineering, Vol. 84, No. 9-10, pp. 1910-1916, 2007.
[2.23]H. Reisinger, G. Steinlesberger, S. Jakschik, M. Gutsche, T. Hecht, M. Leonhard, U. Schroder, H. Seidl and D. Schumann, “A Comparative Study of Dielectric Relaxation Losses in Alternative Dielectrics, IEDM Tech. Dig., 2001, pp. 267-270.
[2.24]A. S. Oates, “Reliability Issues for High-K Gate Dielectrics, IEEE Symp. IEDM Tech. Dig., 2003, pp. 923-926.
[2.25]Z. Xu, L. Pantisano, A. Kerber, R. Degraeve, E. Cartier, Stefan De Gendt, M. Heyns, and G. Groeseneken, “A Study of Relaxation Current in High-k Dielectric Stacks, IEEE Trans. Electron Devices, Vol. 51, No. 3, pp. 402-408, 2004.
[2.26]P. J. Chen, E. Cartier, R. J. Carter, T. Kauerauf, C. Zhao, J. Petry, V. Cosnier, Z. Xu, A. Kerber, W. Tsai, E. Young, S. Kubicek, M. Caymax, W. Vandervorst, S. De Gendt, M. Heyns, M. Cope!, W. F. A. Besling, P. Bajolet, and J. Maes, “Thermal stability and scalability of Zr-aluminate-based high-κ gate stacks, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2002, pp. 192-193.
[2.27]T. Grasser, B. Kaczer, P. Hehenberger, W. Gos, R. O'Connor, H. Reisinger, W. Gustin, and C. Schlunder, “Simultaneous Extraction of Recoverable and Permanent Components Contributing to Bias-Temperature Instability, IEEE Symp. IEDM Tech. Dig., 2007, pp. 801-804.
[2.28]K. Kukli, M. Ritala, Timo Sajavaara, Juhani Keinonen and M. Leskelä, “Comparison of Hafnium Oxide Films Grown by Atomic Layer Deposition from Iodide and Chloride Precursors, Thin Solid Films, Vol. 416, No. 1-2, pp. 72-79, 2002.
[2.29]R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S. A. Sahhaf, and G. Groeseneken, “Review of Reliability Issue in High-k/Metal Gate Stacks, IPFA 15th International Symposium, 2008, pp. 1-6.
[2.30]R. I. Hegde, D. H. Triyoso, P. J. Tobin, S. Kalpat, M. E. Ramon, H.-H. Tseng, J. K. Schaeffer, E. Luckowski, W. J. Taylor, C. C. Capasso, D. C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L. B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R. S. Rai, L. Fonseca, M. Stoker, C. Tracy, B. W. Chan, Y. H. Chiu, and White, B. E., Jr., “Microstructure Modified HfO2 Using Zr Addition with TaxCy Gate for Improved Device Performance and Reliability, IEDM Tech. Dig., 2005, pp. 35-38.
[2.31]Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors, J. Appl. Phys., vol. 101, no. 10 pp. 104503-104503-22, May 2007.
[2.32]H. Irie, K. Kita, K. Kyuno, and A. Toriumi, “In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on (100), (110), and (111) Si, in IEDM Tech. Dig., Dec. 2004, pp. 225-228.
[2.33]N. Mohta, and S. E. Thompson, “Mobility Enhancement, IEEE Circuits and Devices Magazine, vol. 21, pp. 18-23, Sep. 2005.
[2.34]C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, Y. H. Chiu, H. J., Tao, Y. Jin, C. H. Diaz, S. C. Chen, and M. S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application, VLSI Tech. Dig., pp. 56-57, 2004.
[2.35]Dieter K. Schroder, SEMICONDUCTOR MATERIAL AND DEVICE CHARACTERIZATION, Third Edition Arizona State University, Tempe, AZ
[2.36]P. Habas and S. Selberherr, “On the effect of non-degenerate doping of polysilicon gate in thin oxide MOS-devices-analytic modeling, Solid-state Electron. , vol. 33, pp. 1539-1544, 1990
[2.37]F. Stern and W. E. Howard, “Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit, Physical Review B, vol. 163, pp. 816, 1967.
[2.38]E. D. Castro and P. Olivo, “Quantum Effects in Accumulation Layers of Si-SiO2 interfaces in the WKB Effective Mass Approximation, Phys. Stat. Sol., vol. 132, issue 1, pp. 153-163, 1985.
[2.39]K. S. Krisch, J. D. Bude, and L. Manchanda, “Gate Capacitance Attenuation in MOS Devices with Thin Gate Dielectrics, IEEE Electron Device Letters, vol. 17, issue 11, pp. 521-524, 1996.
[2.40]S. Kar and W. E. Dahlke, “Interface state in MOS Structures with 20-40 Å thick SiO2 films on Nondegenerate Si, Solid State Electronics, vol. 15, pp. 221-237, 1972.
[2.41]W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, “Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors, IEEE Electron Device Letters, vol. 20, issue 4, pp. 179-181, 1999.
[2.42]J. R. Hauser and K. Ahmed, “Characterization of Ultrathin Oxides Using Electrical C¬V and I-V Measurements, presented at Characterization and Metrology for ULSI Technology: 1998 International Conference, 1998.
[2.43]C. W. Kuo, Dr. Thesis: Institute of Microelectronics and Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, 2011.
[2.44]P. Dutta and P. M. Horn, “Low-frequency fluctuations in solids: 1/f noise, Rev. Mod. Phys. 53, pp. 497-516, 1981.
[2.45]F. N. Hooge, “T. G. M. Kleinpenning, and L. K. J. Vandamme, Experimental studies on 1/f noise, Rep. Prog. Phys. 44, pp. 479-531, 1981.
[2.46]M. B. Weissman, “1/f noise and other slow, nonexponential kinetics in condensed matter, Rev. Mod. Phys. 60, pp. 537-571, 1988.
[2.47]M. Surdin, “Fluctuations in the thermionic current and the flicker effect, J. Phys. Radium 10, pp. 188-189, 1939.
[2.48]M. von Haartman and M. Östling, Low-Frequency Noise in Advanced MOS Devices, Springer, 2007.
[2.49]F. N. Hooge, “1/f noise sources, IEEE Trans. Electron Devices, vol. 41, issue 11, pp. 1926-1935, 1994.
[2.50]F. N. Hooge, “On the additivity of generation-recombination spectra. Part 2: 1/f noise, Physica B 336, issues 3-4, pp. 236-251, 2003.
[2.51]F. N. Hooge, “1/f noise is no surface effect, Phys. Lett. A 29, issue 3, pp. 139-140 (1969).
[2.52]F. N. Hooge and L. K. J. Vandamme, “Lattice scattering causes 1/f noise, Phys. Lett. A 66, issue 4, pp. 315-316, 1978.
[2.53]F. N. Hooge, “Discussion of recent experiments on 1/f noise, Physica 60, pp. 130-144, 1972.
[2.54]Y. A. Allogo, M. Marin, M. de Murcia, P. Llinares, and D. Cottin, “1/f noise in 0.18 um technology n-MOSFETs from subthreshold to saturation, Solid-State Electronics, vol. 46, issue 7, pp. 977–983, 2002.
[2.55]A. L. McWorther, Semiconductor surface physics (University of Pennsylvania Press, Philadelphia, 1957.
[2.56]E. Simoen, and C. Claeys, “On the flicker noise in submicron silicon MOSFETs, Solid-State Electron. 43, issue 5, pp. 865-882, 1999.
[2.57]G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices, Microelectron. Reliab. 42, issues 4-5, pp. 573-582, 2002.
[2.58]L. K. J. Vandamme, X. Li, and D. Rigaud, “1/f noise in MOS devices, mobility or number fluctuations?, IEEE Trans. Electron Devices 41, issue 11, pp. 1936-1945, 1994.
[2.59]J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures, IEEE Trans. Electron Devices 41, issue 11, pp. 1965-1971, 1994.
[2.60]M. von Haartman, A.-C. Lindgren, P.-E. Hellstrom, B. G. Malm, S.-L. Zhang, and M. Ostling, “1/f noise in Si and Si0.7Ge0.3 pMOSFETs, IEEE Trans. Electron Devices 50, issue 12, pp. 2513-2519, 2003.
[2.61]M. von Haartman, B. G. Malm, and M. Ostling, “Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-k gate dielectrics and TiN gate, IEEE Trans. Electron Devices 53, issue 4, pp. 836-843, 2006.
[2.62]Y. Akue Allogo, M. de Murcia, J. C. Vildeuil, M. Valenza, P. Llinares, and D. Cottin, “1/f noise measurements in n-channel MOSFETs processed on 0.25 μm technology Extraction of BSIM3v3 parameters, Solid-State Electron. 46, issue 3, pp. 361-366, 2002.
[2.63]F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, “Impact of the interfacial layer on the low-frequency noise (1/f) behaviour of MOSFETs with advanced gate stacks, IEEE Electron Device Lett. 27, issue 8, pp. 688-691, 2006.
[2.64]K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors, IEEE Trans. Electron Devices 37, issue 3, pp. 654-665, 1990.
[2.65]G. Ghibaudo, O. Roux, Ch. Nguyen-Duc, F. Balestra, and J. Brini, “Improved analysis of low-frequency noise in field-effect MOS transistors, Phys. Stat. Sol. A 124, issue 2, pp. 571-581, 1991.
[2.66]Fleetwood, D.M., “Border traps in MOS devices, IEEE Trans. Nucl. Sci. 39, issue 2, pp. 269-271, 1992.
[2.67]Fleetwood, D.M., “Fast and slow border traps in MOS devices, IEEE Trans. Nucl. Sci. 43, p. 779, 1996.
[2.68]Dieter K. Schroder, Electrical Characterization of Defects in Gate Dielectrics, Chapter 5 of Defects in Microelectronic Materials and Devices, Boca Raton London New York: Taylor ＆ Francis Group, 2008.
[2.69]Christensson, S., Lundstrom, I., and Svensson, C., “Low-frequency noise in MOS transistors: I-theory, Solid State Electron. 11, issue 9, pp. 797-812, 1968.
[2.70]Tewksbury, T.L. and Lee, H.S., “Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFET’s, IEEE J. Solid State Circ. 29, issue 3, pp. 239-252, 1994.
[2.71]Burstein, E. and Lundquist, S., Tunneling Phenomena in Solids, Plenum Press, New York, 1969.
[2.72]Fu, H.S. and Sah, C.T., “Theory and experiments on surface 1/f noise, IEEE Trans. Electron Dev.ED-19, issue 2, pp. 273-285, 1972.
[2.73]C. D. Young Dr. Thesis: Department of Electrical and Computer Engineering, North Carolina State University, USA, 2003.
[2.74]M. V. Haartman and M. Ostling, Low-Frequency Noise in Advanced MOS Devices. New York: Springer-Verlag, 2007, p. 109.
[2.75]E. P. Vandamme and Lode K. J. Vandamme, “Critical Discussion on Unified 1/f Noise Models for MOSFETs, IEEE Trans. Electron Devices, vol. 47, issue 11, pp. 2146-2152, 2000.
[2.76]S. P. Devireddy, Bigang Min, Zeynep Çelik-Butler, Hsing-Huang Tseng, Philip J. Tobin, and Ania Zlotnicka, “Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric, Microelectron Reliab., vol. 47, issue 8, pp. 1228-1232, 2007.
[2.77]M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states, and low-frequency noise, Adv. Phys., vol. 38, issue 4, pp. 367-468, 1989.
[2.78]Y. -Y. Fan, R.E. Nieh, Jack C. Lee, G. Lucovsky, G.A. Brown, L.F. Register, and Sanjay K. Banerjee, “Voltage- and Temperature-Dependent Gate Capacitance and Current Model: Application to ZrO2 n-channel MOS Capacitor, IEEE Trans. Electron Devices, vol. 49, issue 11, pp. 1969-1978, 2002.
[2.79]S. Machlup, “Noise in semiconductors: spectrum of a two-parameter random signal, J. Appl. Phys. 25, 341-343, 1954.
[2.80]G. Bosman and R. J. J. Zijlstra, “Generation-recombination noise in p-type silicon, Solid-State Electron. 25, issue 4, pp. 273-280, 1982.
[2.81]N. V. Amarasinghe, Z. Çelik-Butler, and A. Keshavarz, “Extraction of oxide trap properties using temperature dependence of random telegraph signals in submicron metaloxide-semiconductor field-effect transistors, J. Appl. Phys. 89, 5526-5532, 2001.
[2.82]M. von Haartman, M. Sandén, M. Östling, and G. Bosman, “Random telegraph signal noise in SiGe heterojunction bipolar transistors, Journal of Applied Physics 92, pp. 4414-4421, 2002.
[2.83]S. Lee, Heung-Jae Cho, Younghwan Son, Dong Seup Lee, and Hyungcheol Shin, “Characterization of Oxide Traps Leading to RTN in High-k and Metal Gate MOSFETs, IEDM Tech. Dig., 2009, pp. 763-766.

Chapter 3
[3.1]R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S.A. Sahhaf, and G. Groeseneken, “Review of Reliability Issue in High-k/Metal Gate Stacks, IPFA 15th International Symposium, 2008, pp. 1-6.
[3.2]R. I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, and White, B.E., Jr., “Microstructure Modified HfO2 Using Zr Addition with TaxCy Gate for Improved Device Performance and Reliability, IEDM Tech. Dig., 2005, pp. 35-38.
[3.3]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, R. Gregory, X.-D. Wang, M. Canonico, D. Roan, E. A. Hebert, K. Kim, J. Jiang, R. Rai, V. Kaushik, S. B. Samavedam, and N. Rochat, “Characteristics of atomic-layer-deposited thin HfZrO2 gate dielectrics, J. Vac. Sci. Technol. B, vol. 25, no. 3, pp. 845-852, 2007.
[3.4]Hyung-Suk Jung, So-Ah Lee, Sang-Ho Rha, S.Y. Lee, H.K. Kim, Do Hyun Kim, Kyu Hwan Oh, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, Nae-In Lee, and Cheol Seong Hwang, “Impacts of Zr Composition in Hf1−xZrxOy Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics, IEEE Trans. Electron Devices, Vol. 58, No. 7, pp. 2094-2103, 2011.
[3.5]C. K. Chiang, J.C. Chang, W.H. Liu, C.C. Liu, J.F. Lin, C.L. Yang, J.Y. Wu, C.K. Chiang, and S.J. Wang, “A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric, Reliability Physics Symposium (IRPS), 2012, Page(s): GD.3.1 - GD.3.4.
[3.6]Y. Nemirovsky, I. Brouk, and C.G. Jakobson, “1/f noise in CMOS transistors for analog applications, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 921-927, 2001.
[3.7]R. I. Hegde, D. H. Triyoso, S. B. Samavedam, and B. E. White Jr., “Hafnium zirconate gate dielectric for advanced gate stack applications, J. Appl. Phys., vol. 101, p. 074113, 2007.
[3.8]H. -S. Jung, Tae Joo Park, Jeong Hwan Kim, S.Y. Lee, J. Lee, Him Chan Oh, Kwang Duck Na, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, Nae-In Lee, and Cheol Seong Hwang, “Systematic Study on Bias Temperature Instability of Various High-k Gate Dielectrics; HfO2, HfZrxOy and ZrO2, IEEE Inter. Reliability Physics Symposium, 2009, pp. 971-972.
[3.9]J. R. Hauser and K. Ahmed, “Characterization of ultra-thin oxides using electrical C-V and I-V measurements, The 1998 international conference on characterization and metrology for ULSI technology, 1998, pp. 235-239.
[3.10]Lode K. J. Vandamme, and F. N. Hooge, “What Do We Certainly Know About 1/f Noise in MOSFETs?, IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3070-3085, 2008.
[3.11]I. M. Hafez, G. Ghibaudo, and F. Balestra, “Flicker noise in metal-oxide-semiconductor transistors from liquid helium to room temperature, J. Appl. Phys., vol. 66, no. 5, p.2211-2213, 1989.
[3.12]•G. Ghibaudo and T. Boutchacha, “Electrical Noise and RTS fluctuations in advanced CMOS devices, Microelectron Reliab., vol. 42, issues 4-5, pp. 573-583, 2002.
[3.13]Lode K. J. Vandamme, “Noise as diagnostic tool for quality and reliability of electronic Devices, IEEE Trans. Electron Devices, vol. 41, issue 11, pp. 2176-2187, 1994.
[3.14]K. K. Hung, P. K. KO, C. Hu, and Y.C. Cheng, “Random telegraph noise of deep-submicrometer MOSFETs, IEEE Electron Device Lett., Vol. 11, pp. 90-92, 1990.
[3.15]Y. T. Huang, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao-Chin Cheng, and Y.C. Cheng, “Dependence of DC Parameters on Layout and Low-Frequency Noise Behavior in Strained-Si nMOSFETs Fabricated by Stress-Memorization Technique, IEEE Electron Device Lett., vol. 31, no. 5, pp. 500-502, May 2010.
[3.16]M. V. Haartman and M. Ostling, Low-Frequency Noise in Advanced MOS Devices. New York: Springer-Verlag, 2007, p. 109.
[3.17]E. P. Vandamme and Lode K. J. Vandamme, “Critical Discussion on Unified 1/f Noise Models for MOSFETs, IEEE Trans. Electron Devices, vol. 47, issue 11, pp. 2146-2152, 2000.
[3.18]S. P. Devireddy, Bigang Min, Zeynep Çelik-Butler, Hsing-Huang Tseng, Philip J. Tobin, and Ania Zlotnicka, “Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric, Microelectron Reliab., vol. 47, issue 8, pp. 1228-1232, 2007.
[3.19]M. J. Kirton and M. J. Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states, and low-frequency noise, Adv. Phys., vol. 38, issue 4, pp. 367-468, 1989.
[3.20]Y.-Y. Fan, R. E. Nieh, J. C. Lee, G. Lucovsky, G. A. Brown, L. F. Register, and S. K. Banerjee, “Voltage- and Temperature-Dependent Gate Capacitance and Current Model: Application to ZrO2 n-channel MOS Capacitor, IEEE Trans. Electron Devices, vol. 49, issue 11, pp. 1969-1978, 2002.
[3.21]M. V. Haartman and M. Ostling, Low-Frequency Noise in Advanced MOS Devices. New York: Springer-Verlag, 2007, p. 47.

Chapter 4
[4.1]Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H.-J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode, IEDM Tech. Dig., 2001, p. 455.
[4.2]H. R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G. A. Brown, C. D. Young, P. M. Zeitzoff, J. Gutt, P. Lysaght, M. I. Gardner, and R. W. Murto, “High-k gate stacks for planar, scaled CMOS integrated circuits, Microelectronic Engineering, vol. 69, issues 2-4,2003, 152-167.
[4.3]J. Robertson, “Band offsets of high dielectric constant gate oxides on silicon, Journal of Non-Crystalline Solids, vol. 303, issue 1, 2002, 94-100.
[4.4]G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations, J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[4.5]H. -S. Jung, J. -H. Lee, S. K. Han, Y. -S. Kim, H J. Lim, M. J. Kim, S. J. Doh, M. Y. Yu, N. -I. Lee, H. -L. Lee, T. -S. Jeon, H. -J. Cho, S. B. Kang, S. Y. Kim, I. S. Park, D. Kim, H. S. Baik, and Y. S. Chung, “A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control, VLSI Tech. Dig. 2005, p. 232-233.
[4.6]International Technology Roadmap for Semiconductors (ITRS), 2005.
[4.7]I. P. Studenyak, M. Kranjcec, O. T. Nahusko, and O. M. Borets, “Influence of Hf→Zr substitution on optical and refractometric parameters of Hf1-xZrxO2 thin films, Thin Solid Films, vol. 476, issue 1, 2005, 137-141.
[4.8]J. K. Schaeffer, L. R. C. Fonseca, S. B. Samavedam, Y. Liang, P. J. Tobin, and B. E. White, “Contributions to the effective work function of platinum on hafnium dioxide, Appl. Phys. Lett. 85, issue 10, pp. 1826-1828, 2004.
[4.9]E. Cartier, F. R. McFeely, V. Narayanan, P. Jamison, B. P. Inder, M. Copel, V. K. Paruchuri, V. Basker, R. Haight, D. Lim, R. Carruthers, T. Shaw, M. Steen, J. Sleight, J. Rubino, H. Deligianni, S. Guha, R. Jammy, and G. Shahidi, “Role of Oxygen Vacancies in VFB/Vt stability of pFET metals on HfO2, VLSI Tech. Dig., 2005, pp. 230-231.
[4.10]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, R. Gregory, X.-D. Wang, M. Canonico, D. Roan, E. A. Hebert, K. Kim, J. Jiang, R. Rai, V. Kaushik, S. B. Samavedam, and N. Rochat, “Characteristics of atomic-layer-deposited thin HfxZr1-xO2 gate dielectrics, Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 25, p. 845, 2007.
[4.11]H.-S. Jung, T. J. Park, J. H. Kim, S. Y. Lee, J. Lee, H. C. Oh, K. D. Na, J.-M. Park, W.-H. Kim, M.-W. Song, N.-I. Lee, C. S. Hwang: Proc. Symp. Reliability Physics, 2009, p. 971.
[4.12]C. K. Chiang, J. C. Chang, W. H. Liu, C. C. Liu, J. F. Lin, C. L. Yang, J. Y. Wu, C. K. Chiang, and S. J. Wang, “A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD Zirconia addition for hafina gate dielectric, Proc. Symp. Reliability Physics, 2012, p.p. GD. 3.1-3.4.
[4.13]Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors for analog applications, IEEE Trans. Electron Devices, vol. 48, issue 5, pp. 921-927, 2001.
[4.14]E. Simoen and C. Claeys: Noise and Fluctuations Control in Electronic Devices, Ed. by A. Balandin, Chapter 8, American Scientific Publishers, 2002.
[4.15]N. Tega, H. Miki, M. Yamaoka, H. Kume, T. Mine, T. Ishida, Y. Mori, R. Yamada, and K. Torii, “Impact of Threshold Voltage Fluctuation Due To Random Telegraph Noise on Scaled-Down SRAM, Proc. Symp. Reliability Physics, 2008, p. 541-546.
[4.16]S. Lee, H.-J. Cho, Y. Son, D. S. Lee, and H. Shin, “Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs, IEDM Tech. Dig., 2009, p. 763-766.
[4.17]B. C. Wang, S. L. Wu, Y. Y. Lu, S. J. Chang, J. F. Chen, S. C. Tsai, C. H. Hsu, C. W. Yang, C. G. Chen, O. Cheng, and P. C. Huang, “Comparison of the trap behavior between ZrO2 and HfO2 gate stack nMOSFETs by 1/f noise and random telegraph noise, IEEE Electron Device Letters, pp. 151-153, 2013.
[4.18]S. C. Tsai, S. L. Wu, B. C. Wang, S. J. Chang, C. H. Hsu, C. W. Yang, C. M. Lai, C. W. Hsu, O. Cheng, P. C. Huang, and J. F. Chen, “Low-frequency noise characteristics for various ZrO2-added HfO2-based 28-nm high-k/metal-gate nMOSFETs, IEEE Electron Device Letters, pp. 834-836, 2013.
[4.19]Shih Chang Tsai, San Lein Wu, Chung Yi Wu, Chien Wei Huang, Yu Ying Lu, Bo Chin Wang, Shoou Jinn Chang, Jone Fang Chen, Osbert Cheng, and Po Chin Huang: 2012 International Conference on Solid State Devices and Materials, 2012, p. 120.
[4.20]E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, and M. Copel: AVS Topical Conf. on Atomic Layer Deposition, 2001.
[4.21]D. H. Triyoso, R. I. Hegde, B. E. White, and P. J. Tobin, “Physical and electrical characteristics of atomic-layer-deposited hafnium dioxide formed using hafnium tetrachloride and tetrakis, J. Appl. Physics, 97, 2005.
[4.22]J. R. Hauser and K. Ahmed “Characterization of ultra-thin oxides using electrical C-V and I-V measurements, Proc. Int. Conf. Characterization and metrology for ULSI technology, 1998, p. 235.
[4.23]M. Toita, L. K. J. Vandamme, S. Sugawa, A. Teramoto, T. Ohmi, “Geometry and Bias Dependence of Low-Frequency Random Telegraph Signal and 1/f Noise Levels in Mosfets, Fluct. Noise Lett., vol. 5, issue 4, pp. 539, 2005.
[4.24]M. Sato, N. Umezawa, N. Mise, S. Kamiyama, M. Kadoshima, T. Morooka, T.Adachi, T.Chikyow, K. Yamabe, K. Shiraishi, S. Miyazaki, A. Uedono, K. Yamada, T. Aoyama, T. Eimori, Y. Nara, and Y. Ohji, “Physical understanding of the reliability improvement of dual high-k CMOSFETs with the fifth element incorporation into HfSiON gate dielectrics, VLSI Tech. Dig., 2008, p. 66-67.
[4.25]L. K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know About 1/f Noise in MOSTs?, IEEE Trans. Electron Devices ,vol. 55, issue 11, 2008.
[4.26]L. K. J. Vandamme, “Noise as a diagnostic tool for quality and reliability of electronic devices, IEEE Trans. Electron Devices, vol. 41, issue 11, pp. 2176-2187, 1994.
[4.27]F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, and C. Claeys, “Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks, IEEE Electron Device Letters, vol. 27, issue 8, pp. 688-691, 2006.
[4.28]G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices, Microelectron. Reliab. vol. 42, issues 4-5, pp. 573-582, 2002.
[4.29]Po Chin Huang, San Lein Wu, Shoou Jinn Chang, Yao Tsung Huang, Jone F. Chen, Chien Ting Lin, Mike Ma, and Osbert Cheng, “Characteristics of Si/SiO2 Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method, IEEE Trans. Electron Devices, vol. 58, issue 6, 2011, 1635-1642.
[4.30]E. P. Vandamme and Lode K. J. Vandamme, “Critical discussion on unified 1/f noise models for MOSFETs, IEEE Trans. Electron Devices, vol. 47, issue 11, pp. 2146-2152, 2000.
[4.31]K. Kandiah, M. O. Deighton, and F. B. Whiting, “A physical model for random telegraph signal currents in semiconductor devices, J. Appl. Phys. 66, p. 937, 1989.
[4.32]N. V, Amarasingh, Z.Celik-Butler, A. Zlotnicka, and F. Wang, “Model for random telegraph signals in sub-micron MOSFETS, Solid-State Electron. vol. 47, issue 9, pp. 1443-1449, 2003.
[4.33]B. C. Wang, S. L. Wu, C. W. Huang, Y. Y. Lu, S. J. Chang, Y. M. Lin, K. H. Lee, and O. Cheng, “Characterization of Oxide Tarps in 28 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Tip-Shaped SiGe Source/Drain Based on Random Telegraph Noise, J. Appl. Phys. 51, 02BC11, 2012.
[4.34]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors, Rep. Prog. Phys. 69, p. 327, 2006.
[4.35]M.K. Bera, C.K. Maiti, “Reliability of ultra thin ZrO2 films on strained-Si, Microelectron. Reliab. vol. 48, issue 5, pp. 682-692, 2008.

Chapter 5
[5.1]G. D. Wilk, R. M. Wallace and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations, J. Appl. Phys., vol. 89, pp. 5243-5275, 2001.
[5.2]Robertson, J., “High dielectric constant oxides, Eur. Phys. J. Appl. Phys., vol. 28, issue 3, 265-291, 2004.
[5.3]Hubbard, K.J. and Schlom, D.G., “Thermodynamic stability of binary oxides in contact with Si, J. Mater. Res., vol. 11, issue 11, 2757-2776, 1996.
[5.4]Robertson, J., “Band offsets of wide-band-gap oxides and implications for future electronic devices, J. Vac. Sci. Technol., B18, 1785, 2000.
[5.5]E.P. Gusev, D.A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P.C. Jamison, D.A. Neumayer, M. Copel, M.A. Gribelyuk, H. Okorn-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L.-A. Ragnarsson, P. Ronsheim, K. Rim, R.J. Fleming, A. Mocuta, and A. Ajmera, “Ultrathin high-K gate stacks for advanced CMOS devices, Tech Digest—Int. Electron Devices Meeting, 455, 2001.
[5.6]R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S.A. Sahhaf, and G. Groeseneken, “Review of reliability issue in high-k/metal gate stacks, in Proc. 15th Int. Symp. Phys. Failure Anal.Integr. Circuits, Jul. 2008, pp. 1–6.
[5.7]R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, and White, B.E., Jr., “Microstructure modified HfO2 using Zr addition with TaxCy gate for improved device performance and reliability, in Proc. IEEE Int. Electron Devices, Dec. 2005, pp. 35–38.
[5.8]D. H. Triyoso, R. I. Hegde, J. K. Schaeffer, R. Gregory, X.-D. Wang, M. Canonico, D. Roan, E. A. Hebert, K. Kim, J. Jiang, R. Rai, V. Kaushik, S. B. Samavedam, and N. Rochat, “Characteristics of atomic-layer-deposited thin HfxZr1-xO2 gate dielectrics, J. Vac. Sci. Technol. B, vol. 25, no. 3, pp. 845–852, May 2007.
[5.9]H.-S. Jung, S.-A. Lee, S.-H. Rha, S. Y. Lee, H. K. Kim, Do Hyun Kim, Kyu Hwan Oh, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, Nae-In Lee, and Cheol Seong Hwang, “Impacts of Zr composition in Hf1-xZrxOy gate dielectrics on their crystallization behavior and bias temperature-instability characteristics, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 2094–2103, Jul. 2011.
[5.10]C. K. Chiang, J. C. Chang, W. H. Liu, et al., “A comparative study of gate stack material properties and reliability characterization in MOS transistors with optimal ALD zirconia addition for hafinia gate dielectric, in Proc. Rel. Phys. Symp., Apr. 2012, pp. GD.3.1–GD.3.4.
[5.11]Y. Nemirovsky, I. Bloom, and Y. Nemirovsky, “1/f noise in CMOS transistors for analog applications, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 921–927, May 2001.
[5.12]E. P. Gusev, E. Cartier, D. A. Buchanan, M. Gribelyuk, and M. Copel: AVS Topical Conf. on Atomic Layer Deposition, 2001.
[5.13]D. H. Triyoso, R. I. Hegde, B. E. White, and P. J. Tobin, “Physical and electrical characteristics of atomic-layer-deposited hafnium dioxide formed using hafnium tetrachloride and tetrakis (ethylmethylaminohafnium), J. Appl. Physics, 97, 2005.
[5.14]J. R. Hauser and K. Ahmed, “Characterization of ultra-thin oxides using electrical C-V and I-V measurements, Proc. Int. Conf. Characterization and metrology for ULSI technology, 449, 1998, p. 235.
[5.15]Shih Chang Tsai, San Lein Wu, Chung Yi Wu, Chien Wei Huang, Yu Ying Lu, Bo Chin Wang, Shoou Jinn Chang, Jone Fang Chen, Osbert Cheng, and Po Chin Huang: 2012 International Conference on Solid State Devices and Materials, 2012, p. 120.
[5.16]Shih-Chang Tsai, San-Lein Wu, Po-Chin Huang, Bo-Chin Wang, Kai-Shiang Tsai, Tsung-Hsien Kao, Chih-Wei Yang, Cheng-Guo Chen, Osbert Cheng, Yean-Kuen Fang, Shoou-Jinn Chang, and Jone-Fang Chen, “Investigation of Trap Properties of Hf0.83Zr0.17O2 High-k Gate Stack pMOSFETs by Low-frequency (1/f ) Noise and RTN Analyses, JPN. J. Appl. Phys., vol. 53, 08LB03, 2014.
[5.17]Bo Chin Wang, San Lein Wu, Yu Ying Lu, Shoou Jinn Chang, Jone Fang Chen, Shih Chang Tsai, Che Hua Hsu, Chih Wei Yang, Cheng Guo Chen, O. Cheng, and Po Chin Huang, “Comparison of the Trap Behavior Between ZrO2 and HfO2 Gate Stack nMOSFETs by 1/f Noise and Random Telegraph Noise, EDL, vol. 34, issue 2, pp. 151-153, 2013.
[5.18]E. P. Vandamme and Lode K. J. Vandamme, “Critical Discussion on Unified 1/f Noise Models for MOSFETs, IEEE Trans. Electron Devices vol. 47, no. 11, p. 2146, 2000.
[5.19]Lucovsky, G., “Transition from thermally grown gate dielectrics to deposited gate dielectrics for advanced silicon devices: A classification scheme based on bond ionicity, J. Vac. Sci. Technol., A19, 1553, 2001.
[5.20]Robertson, J., “Interfaces and defects of high-K oxides on silicon, Solid-State Electron., vol. 49, issue 3, 283-293, 2005.
[5.21]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors, Rep. Prog. Phys. 69, p. 327, 2006.
[5.22]J. Robertson, K. Xiong and B. Falabretti, “Point Defects in ZrO2 High-k Gate Oxide, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, vol. 5, no. 1, 84-89, MARCH 2005.
[5.23]M. K. Bera and C. K. Maiti, “Reliability of ultra thin ZrO2 films on strained-Si, Microelectron. Reliab. vol. 48, issue 5, pp. 682-692, 2008.

Chapter 6
[6.1]S. C. Tsai, S. L. Wu, B. C. Wang, S. J. Chang, C. H. Hsu, C. W. Yang, C. M. Lai, Chia Wei Hsu, O. Cheng, P. C. Huang, and J. F. Chen, “Low-Frequency Noise Characteristics for Various ZrO2 - Added HfO2 - Based 28-nm High- k/Metal-Gate nMOSFETs, Electron Device Lett. 34, issue 7, 834-836, 2013.
[6.2]G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices, Microelectron. Reliab. 42, issues 4-5, 573-582, 2002.
[6.3]Lode K. J. Vandamme and F. N. Hooge, “What Do We Certainly Know About 1/f Noise in MOSTs?, IEEE Trans. Electron Devices 55,issue 11, 3070-3085, 2008.
[6.4]C. Hu, “Device challenges and opportunities, VLSI Tech. Dig., 2004, p. 4-5.
[6.5]T. J. Wang, C. H. Ko, H. N. Lin, S. J. Chang, S. L. Wu, T. M. Kuan, and W. C. Lee, “Investigation of Metallized Source/Drain Extension for High-Performance Strained nMOSFETs, IEEE Trans. Electron Devices 55, issue 11, 3221-3226, 2008.
[6.6]S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced strained-Si: extending the CMOS roadmap, IEEE Trans. Electron Devices 53, issue 5, 1010-1020, 2006.
[6.7]E. Simoen, P. Verheyen, A. Shickova, R. Loo, and C. Claeys, “On the Low-Frequency Noise of pMOSFETs With Embedded SiGe Source/Drain and Fully Silicided Metal Gate, Electron Device Lett., 28, 987-989, 2007.
[6.8]C. W. Kuo, S. L. Wu, S. J. Chang, H. Y. Lin, and Y. P. WangShang Chao Hung, “Investigation of interface characteristics in strained-Si nMOSFETs, Solid-State Electron., 53, 897-900, 2009.
[6.9]B. C. Wang, S. L. Wu, C. W. Huang, Y. Y. Lu, S. J. Chang, Y. M. Lin, K. H. Lee, and Osbert Cheng, “Correlation Between Random Telegraph Noise and 1/f Noise Parameters in 28-nm pMOSFETs With Tip-Shaped SiGe Source/Drain, IEEE Electron Device Lett., 33, 928-930, 2012.
[6.10]H. -S. Jung, J. -H. Lee, S. K. Han, Y. -S. Kim, H J. Lim, M. J. Kim, S. J. Doh, M. Y. Yu, N. -I. Lee, H. -L. Lee, T. -S. Jeon, H. -J. Cho, S. B. Kang, S. Y. Kim, I. S. Park, D. Kim, H. S. Baik, and Y. S. Chung, “A highly manufacturable MIPS (metal inserted poly-Si stack) technology with novel threshold voltage control, VLSI Tech. Dig., 2005, p. 232-233.
[6.11]B. C. Wang, S. L. Wu, C. W. Huang, Y. Y. Lu, S. J. Chang, Y. M. Lin, K. H. Lee, and Osbert Cheng, “Characterization of Oxide Tarps in 28 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Tip-Shaped SiGe Source/Drain Based on Random Telegraph Noise, Jpn, J. Appl. Phys., 51, 02BC11, 2012.
[6.12]L.-Å. Ragnarsson, Z. Li, J. Tseng, T. Schram, E. Rohr, M. J. Cho, T. Kauerauf, T. Conard, Y. Okuno, B. Parvais, P. Absil, S. Biesemans, and T. Y. Hoffmann, “Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization, IEDM Tech. Dig., 2009, p. 663.
[6.13]J. K. Schaeffer, S. B. Samavedam, D. C. Gilmer, V. Dhandapani, P. J. Tobin, J. Mogab, B.-Y. Nguyen, B. E. White, Jr., S. Dakshina-Murthy, R. S. Rai, Z.-X. Jiang, R. Martin, M. V. Raymond, M. Zavala, L. B. La, J. A. Smith, R. Garcia, D. Roan, M. Kottke, and R. B. Gregory, “Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics, J. Vac. Sci. Technol., B 21, 11, 2003.
[6.14]J. R. Hauser and K. Ahmed, “Characterization of ultra-thin oxides using electrical C-V and I-V measurements, in Proc. Int. Conf. Characterizat. Metrol. ULSI Technol., 1998, pp. 235–239.
[6.15]P. C. Huang, S. L. Wu, S. J. Chang, Y. T. Huang, J. F. Chen, C. T. Lin, M. Ma, and O. Cheng, “Characteristics of Interface Properties for CMOS Fabricated on Hybrid Orientation Substrate Using Amorphization/Templated Recrystallization (ATR) Method, IEEE Trans. Electron Devices, 58, 1635, 2011.
[6.16]C. W. Kuo, S. L. Wu, S. J. Chang, Y. T. Huang, Y. C. Cheng, and O. Cheng, “Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors, Appl. Phys. Lett., 97, 123501, 2010.
[6.17]J. J. Y. Kuo, W. P. N. Chen, and P. Su, “ Impact of uniaxial strain on low-frequency noise in nanoscale pMOSFETs, IEEE Electron Device Lett., 30, 672-674, 2009.
[6.18]C. Y. Cheng, Y. K. Fang, J. C. Hsieh, H. Hsia, Y. M. Sheu, W. T. Lu, W. M. Chen, and S. S. Lin, “Investigation and Localization of the SiGe Source/Drain (S/D) Strain-Induced Defects in PMOSFET With 45-nm CMOS Technology, IEEE Electron Device Lett., 28, 408-411, 2007.
[6.19]S. M. Sze and Kwok K. Ng, Physics of Semiconductor Devices, Third Edition, A John Wiley ＆ Sons, Inc., 2007.
[6.20]X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs, Proc. Int. Electron Devices Semicond. Technol., 2007, p. 149-152.
[6.21]M. v. Haartman and M. Östling: Low-Frequency Noise in Advanced MOS Devices (Springer, Heidelberg, 2007) p. 47.
[6.22]H. F. Chiu, S. L. Wu, Y. S. Chang, S. J. Chang, P. C. Huang, J. F. Chen, S. C. Tsai, C. M. Lai, C. W. Hsu, and O. Cheng, “Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization, Jpn, J. Appl. Phys., 52, 04CC22, 2013.
[6.23]S. Lee, Heung-Jae Cho, Younghwan Son, Dong Seup Lee, and Hyungcheol Shin, “Characterization of Oxide Traps Leading to RTN in High-k and Metal Gate MOSFETs, IEDM Tech. Dig., 2009, pp. 763-766.
[6.24]S. C. Tsai, S. L. Wu, P. C. Huang, B. C. Wang, K. S. Tsai, T. H. Kao, C. W. Yang, C. G. Chen, K. Y. Lo, O. Cheng, Y. K. Fang, S. J. Chang, and J. F. Chen: 2013 International Workshop on Dielectric Thin Films For Future Electron Devices Science and Technology, 2013, p. 87.
[6.25]V. Vartanian, S. Zollner, A. V.-Y. Thean, T. White, B.-Y. Nguyen, L. Prabhu, D. Eades, S. Parsons, H. Desjardins, K. Kim, Z.-X. Jiang, V. Dhandapani, J. Hildreth, R. Powers, G. Spencer, N. Ramani, M. Kottke, M. Canonico, X.-D. Wang, L. Contreras, D. Theodore, R. Gregory, and S. Venkatesan, “Metrology Challenges for 45-nm Strained-Si Device Technology, IEEE Trans. Semiconductor Manufacturing, 19, 381-390, 2006.
[6.26]S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for performance enhancement of Si MOSFETs, in IEDM. Tech. Dig., 1997, p. 219-222.
[6.27]P. Srinivasan, E. Simoen, L. Pantisano, C. Claeys, and D. Misrab, “Low-Frequency  ( 1 ∕ f )  Noise Performance of n- and p-MOSFETs with Poly- Si ∕ Hf -Based Gate Dielectrics, J. Electrochem. Soc., 153, G324, 2006.

Chapter 7
[7.1]M J Kirton, and M J Uren, “Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/f) noise, ADVANCES IN PHYSICS, Vol 38, n0 4, PP 367-468, 1989.
[7.2]E. Simoen, J. Mitard, G. Hellings, G. Eneman, B. De Jaeger, L. Witters, B. Vincent, R. Loo, A. Delabie, S. Sioncke, M. Caymax, and C. Claeys, “Challenges and opportunities in advanced Ge pMOSFETs, Mater. Sci. Semicond. Process, vol. 15, no. 6, pp. 588–600, Dec. 2012.
[7.3]M. Hong, J. R. Kwo, P. Tsai, Y. Chang, M.-L. Huang, C. Chen, and T. Lin, “III-V metal-oxide-semiconductor field-effect transistors with high κ dielectrics, Jpn. J. Appl. Phys., vol. 46, no. 5B, pp. 3167–3180, May 2007.