臺灣博碩士論文加值系統

本論文提出一個基於邊緣強化超解析度演算法。此演算法可分為邊緣強化內插法與高頻增強兩個部份，而內插法的部份又可以再區分為對角線與水平垂直內插兩個步驟。在第一步驟中，先針對對角線上未知的像素進行內插，藉由分辨邊緣方向預先決定使用的參考像素與是否參考鄰近像素梯度值。至於沒有被填滿的像素，則會在第二步驟中，依同樣預先決定的方法估算。在兩個步驟中，使用衰減函數，以避免混疊效應，再加上增強高頻部分，來還原高解析度影像。實驗結果顯示，使用此演算法之峰值訊號雜訊比可達到平均值為28.448 dB，而其結構相似度平均值可達到0.8740。此外，本論文亦提出硬體架構，將演算法實現在Altera的FPGA板上，共使用約6千個邏輯元件，運作速度達到216 MHz。

In this thesis, an edge-enhanced super resolution algorithm is proposed. The algorithm consists of two major parts, edge-enhanced interpolation, and high frequency enhancement. The interpolation method can be further separated into two steps. In the first step, the unknown pixels in the diagonal direction are first classified into with and without edge which will deal with an early skipped interpolation and a strict interpolation method, respectively. In the second step, horizontal or vertical interpolation method is adopted to fill up the reminding pixels in horizontal or vertical direction. After interpolations, a high frequency enhancement method with a degradation function is finally applied to avoid the aliasing effect and enhancing the high frequency region. Moreover, a hardware architecture is designed for the proposed algorithm to reduce execution time. Experimental results shows that the proposed algorithm achieves 28.448 dB in the average PSNR and 0.8740 in the average SSIM. Besides, the VLSI architecture can achieve 216 MHz with 6.2 k logic elements on Altera FPGA.

Abstract (Chinese) i
Abstract (English) ii
Acknowledgements iii
Table of Contents iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 3
Chapter 2 Basic Concepts of Super Resolution 4
2.1 The Basic Concept of Image Sampling 4
2.2 Related Work 8
2.2.1 Image interpolation algorithms 8
2.2.1.1 Nearest neighbor interpolation 9
2.2.1.2 Bilinear interpolation 11
2.2.1.3 Bi-cubic interpolation 13
2.2.2 Edge detecting model 16
Chapter 3 The Proposed Super Resolution Algorithm 18
3.1 Overview of the Proposed Super Resolution Algorithm 19
3.2 Edge-enhanced Interpolation Method 19
3.2.1 Diagonal interpolation 21
3.2.2 Vertical/horizontal interpolation 26
3.3 High frequency enhancement 29
3.4 Hardware design of the proposed method 30
3.4.1 Data buffer and controller 31
3.4.2 Weight generator 32
3.4.3 Interpolation unit 34
Chapter 4 Simulation Results and Discussion 35
4.1 Simulation Environment Settings 36
4.2 Parameter Settings and Simulation Results 39
4.2.1 Correlation parameter selection 40
4.2.2 Threshold value selection 41
4.2.3 Control parameter selection 42
4.2.4 Edge enhanced parameters selection 43
4.3 Simulation Results for the Proposed Functions 45
4.4 Simulation Results for the Hardware Implementation 52
Chapter 5 Conclusion and Future Work 55
5.1 Conclusion 55
5.2 Future Work 56
References 58
Publication List 60

[1] D. Zhou, X. Shen, and W. Dong, “Image zooming using directional cubic convolution interpolation, IET Image Process., vol. 6, pp. 627–634, Aug. 2012.
[2] X. Li and M. T. Orchard, “New edge-directed interpolation, IEEE Trans. Image Process., vol. 10, pp. 1521–1527, Oct. 2001.
[3] Y. Luo, S. Liu, and H. Zhu, “Edge-directed interpolation based on canny detector, in Proc. IEEE Int. Conf. Mechatron. Autom., Aug. 2011, pp. 698–702.
[4] A. Temizel and T. Vlachos, “Wavelet domain image resolution enhancement using cycle-spinning, Electron. Lett., vol. 41, pp. 119–121, Feb. 2005.
[5] M. Irani and S. Peleg, “Improving resolution by image registration, CVGIP Graph. Models. Image Process., vol. 53, pp. 231–239, June 1991.
[6] W. Dong, L. Zhang, G. Shi, and X. Wu, “Nonlocal back-projection for adaptive image enlargement, in Proc. IEEE Int. Conf. Image Process., Nov. 2009, pp. 349–352.
[7] T.S. Huang, R.Y. Tsai, “Multi-frame image restoration and registration, in Advances in Computer Vision and Image Processing, 2nd ed, vol. 1, T.S. Huang, Ed. Greenwich, CT: JAI Press, 1984, pp. 317–339.
[8] H. Zhang, Y. Zhang, H. Li, and T. S. Huang, “Generative bayesian image super resolution with natural image prior, IEEE Trans. Image Process., vol. 21, pp. 4054–4067, Sep. 2012.
[9] S. Fifman, “Digital rectification of ERTS multispectral imagery, in Proc. Symp. Significant Results Obtained from ERTS-1, Nov. 1995, pp. 1131–1142.
[10] R. C. Gonzalez and R. E. Woods, Digital Image Processing. Reading, MA: Addison-Wesley, 1992.
[11] H. S. Hou and H. Andrews, “Cubic splines for image interpolation and digital filtering, IEEE Trans. Acoust., Speech, Signal Process., vol. 26, pp. 508–517, Dec. 1978.
[12] M. Elad, “On the origin of the bilateral filter and ways to improve it, IEEE Trans. Image Process., vol. 11, pp. 1141–1151, Dec. 2012.
[13] G. Ramponi, “Warped distance for space-variant linear image interpolation, IEEE Trans. Image Process., vol. 8, pp.629–639, May 1999.
[14] P. Y. Chen, C. Y. Lien, and C. P. Lu, “VLSI implementation of an edge-oriented image scaling processor, IEEE Trans. Very Large Scale Integr. Syst., vol. 17, pp.1275–1284, Sep. 2009.
[15] Y. S. Wu, “A super resolution algorithm based on iterative edge-directional predictions, M.S. thesis, National Cheng Kung University, Taiwan, July 2014.
[16] C. H. Kim, S. M. Seong, J. A. Lee, and L. S. Kim, “Winscale: animage-scaling algorithm using an area pixel model, IEEE Trans. Circuits Syst. Video Technol., vol. 13, pp.549–553, June 2003.
[17] Andreadis and A. Amanatiadis, “Digital imagescaling, in Proc. IEEE Instrum. Meas. Technol. Conf., May 2005, pp.2028–2032.
[18] C. C. Lin, M. H. Sheu, H. K. Chiang, W. K. Tsai, and Z. C. Wu, “Real-time FPGA architecture of extended linear convolution for digital imagescaling, in Proc. IEEE Int. Conf. Field-Programmable Technol., Dec. 2008, pp.381–384.
[19] S. L. Chen, “VLSI implementation of a low cost high quality image scaling processer, IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 60, pp.31–35, Jan. 2013.