臺灣博碩士論文加值系統

本論文研究能使三角積分調變器朝向寬頻發展的低功率技術，另外亦提出兩種放大器的技術來分別改善由運算放大器共享技術引起的記憶效應，與節省在離散切換電容電路操作時不必要的放大器功耗。

在三角積分調變器的部分，架構與電路上皆提出了新的技術以達到低功耗的目的。所提出的三個三階的三角積分器架構可以最小化所需使用到的運算放大器數目並最大化運算放大器功率的使用率。這些架構延長了關鍵的回授路徑時間變為半個時脈週期，使得其它低速但是高功耗效率的類比數位轉換器架構可以被採用做為量化器，不再侷限於只能使用快閃式架構。為了處理回授的數位類比轉換器元件之間的不匹配問題，本論文提出ㄧ個簡化的資料加權平均演算法來減輕其非線性現象，且與傳統資料加權平均演算法相比，其硬體實現亦較為簡單。第一個設計例子使用ㄧ個雙重積分器架構做為第二級積分器，用以提升前兩級積分器電路採用運算放大器共享技術的效力。而量化器採用無負載技術的四位元的循環式類比數位轉換器，並且與主動加法器共享同一運算放大器。對照於需要四個運算放大器的傳統三角積分調變器，所提出之架構包含主動加法器與量化器時，只使用了兩個運算放大器。第二個設計例子簡化了第一個設計的調變器架構，在整個電路中僅僅使用了一個運算放大器便能完成三階的雜訊整形能力。為了在不使用功率可觀的放大器狀態下實現量化器的加法器，我們改為採用結合於四位元逐漸趨近式類比數位轉換器電容陣列的電容式被動加法器。第三個設計例子把主動加法器與最後一級的積分器合併，並利用時間共享技術於第二與第三級的積分器，使得在同一時脈相位下可共同使用ㄧ個運算放大器。又因為第一級積分器的操作相位不同於第二與第三級的相位，如此ㄧ來，三個積分器只需要用到ㄧ個運算放大器，大幅降低了功率消耗。

在放大器的部分，共有三個技術被提出：第一個技術為可分離式的放大器，它擁有兩個組態模式，其可拆解為兩個相同尺寸的小放大器或結合成ㄧ個大的放大器。此法可以增加放大器功率的使用率並減少共享級電路的殘餘訊號。在ㄧ個雙相位時脈系統中，此放大器在其中ㄧ個相位時可以分解為兩個相同小放大器同時給兩個電路去應用；而在另一個相位時，此兩個放大器可合併為ㄧ個大的放大器給另個電路使用。相比於傳統的運算放大器共享技術，在分解模式下，可以達到更高功耗效率的放大器安排。進而，基於這個可分離式放大器的概念，ㄧ個部分可開關的放大器被提出來避免切換電容電路中於任ㄧ操作時脈的過剩功率消耗。在此架構放大器中，可以開關的部分與持續導通的部分之比例設定可以被調整，用以最佳化放大器在整個時脈的平均功率消耗。最後，我們還提出了一個分裂電容式且時間對準的具相關性雙重取樣技術，此方法可以解決傳統具相關性雙重取樣技術所遭遇的雙倍電容負載及一次運轉需要三個時脈相位才能完成的問題。此外，在預估計的時脈相位時所需的額外電容組合與用來儲存有限增益誤差的電容都可以被省略。

This dissertation investigates low-power technologies for delta-sigma modulators (DSMs) toward the wide-bandwidth development and additionally presents two amplifier’s technologies respectively for improving the memory effect, resulting from operational amplifier (opamp) sharing, and saving the unnecessary opamp power for the discrete-time switched-capacitor (SC) circuits.

For the DSM part, the techniques both on architectural and circuit level to achieve the low-power purpose are presented. The proposed three third-order low-distortion DSM structures are capable of minimizing the number of used opamps and maximizing the utilization of their power; they prolong the critical feedback path timing to be half clock period, leading to that other low-speed but high power-efficient analog-to-digital converter (ADC) types can be adopted as a quantizer and not be confined to the flash ADC anymore. For dealing with the mismatch of the feedback digital-to-analog converter (DAC), a simplified data weighted averaging (SDWA) algorithm is presented to alleviate not only the nonlinearity, but also the hardware implementation compared with the conventional DWA. In the first design, a double integrator structure is built as the second integrator to enhance the efficiency of opamp sharing applied between the first two integrators. A 4-bit cyclic ADC with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. In contrast to the conventional DSM requiring four opamps, the proposed structure just employs two opamps including the active adder and quantizer. The second design is to simplify the modulator structure of the first one and just uses single opamp to accomplish third-order noise-shaping ability in the whole circuit. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the DAC array of a 4-bit successive-approximation-type quantizer, is used. The third design merges the active adder into the last integrator and exploits the timing-sharing technique between the second and third integrators during one clock phase. Further, since the operation phase of the first integrator is different to those of the second and third ones, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly.

In the amplifier part, three techniques are proffered: The first is a splitable amplifier that can be either decomposed into two identical halves or merged for enhancing the utilization of amplifier power and alleviate the residue of the shared circuit stage. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one of the two phases simultaneously for use in two circuits and the two small amplifiers can be merged into one amplifier in the other phase for another circuit. Compared with conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in split mode. Furthermore, a partial switchable amplifier, based on the concept of the splitable amplifier, is proposed to avoid the superfluous power consumption during one of operation phases in SC circuits. Depending on the required amplifier bandwidth, the selection of the proportion of the switchable part to the always on part can be used to optimize power consumption. Finally, we propose a split-capacitor time-aligned correlated double sampling (CDS) technique that can resolve both the problems of the double capacitance loading and three phases per operation in conventional CDS technique. In addition, the capacitor set during prediction phase and extra capacitor for storing the finite gain error can be saved.

Abstract (Chinese) i
Abstract (English) iii
Acknowledgement vii
Table of Contents xi
List of Tables xiv
List of Figures xv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Dissertation Contribution 3
1.3 Organization of Dissertation 4
Chapter 2 Low-Distortion and Power-Efficient Delta-Sigma Modulators: A Review of Literature 5
2.1 Background 5
2.2 Low-Distortion DSM Structures 7
2.3 Prior Arts in Low Power DSMs 12
Chapter 3 Low Power Delta-Sigma Modulator Designs 25
3.1 Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing 25
3.1.1 Proposed Modulator Architecture 26
3.1.2 Circuit Implementation and Design Considerations 31
3.1.3 Simulation Results 42
3.2 Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder 45
3.2.1 Proposed Modulator Architecture 45
3.2.2 Exploration of the Opamp-Sharing Memory Effect 50
3.2.3 Circuit Implementation and Design Considerations 55
3.2.4 Simulation and Measurement results 64
3.3 Third-Order Delta-Sigma Modulator with Timing-Sharing Opamp-Sharing Technique 69
3.3.1 Proposed Topology 70
3.3.2 Circuit Implementation 74
3.3.3 Simulation Results 81
3.4 Simplified Data Weighted Averaging Algorithm 84
3.4.1 Overview of Conventional DWA Algorithm 86
3.4.2 Introduction of Merged-Capacitor Switching (MCS) Technique 87
3.4.3 Proposed SDWA algorithm 89
3.4.4 Circuit implementation 92
3.5 Summary 97
Chapter 4 Design Techniques of Splitable, Partial Switchable Amplifiers, and Split-Capacitor TA-CDS for Opamp Based Circuits 99
4.1 Background 99
4.1.1 Overview of memory effect 100
4.1.2 Overview of Correlated Double Sampling (CDS) Technique 104
4.2 Splitable Amplifier Technique and Its Application for Opamp Sharing to Cancel Memory Effect 113
4.2.1 Concept and Design Example 113
4.2.2 Analysis of Gain and Bandwidth 122
4.2.3 Circuit Implementation and Simulation Results 124
4.3 Partial Switchable Amplifier Technique 139
4.3.1 Concept and Design Example 140
4.3.2 Circuit Implementation and Simulation Results 142
4.4 Split-Capacitor Time-Aligned Correlated Double Sampling Technique 148
4.4.1 Concept and Operation 150
4.4.2 Circuit Implementation and Simulation Results 154
4.5 Summary 160
Chapter 5 Conclusion and Future Work 161
5.1 Conclusion 161
5.2 Future work 163
Appendices 164
References 170
Publication and Award 179

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