臺灣博碩士論文加值系統

在蕭特基奈米線電晶體製作中，退火製程具有關鍵的影響，將決定金屬汲/源極的有效蕭特基能障及奈米線元件的電壓電流特性。此論文探討利用微波退火技術來實現具金屬矽化物汲/源極之奈米線電晶體，包括本質和具摻雜析離層的蕭特基奈米線電晶體和無接面奈米線電晶體，並進行相關的電物性分析。採用微波退火製程相較於傳統快速升溫退火製程而言，具備重要的低溫優點及退火有效性，能較易於控制金屬矽化物汲/源極接面製作以及高濃度摻雜析離層的形成。
本於論文研究中，採用矽化鎳、矽化鐿及矽化鈦三種金屬矽化物進行探討，並應用側壁式氧化層來製作奈米線，成功的實現出在低溫微波退火下具金屬矽化物汲源極的蕭特基奈米線電晶體。由研究結果來看，微波退火可在最低功率之80%、200%及500%條件下，經過300秒的退火時間，製作出具低片電阻值特性的矽化鎳、矽化鐿及矽化鈦。並可在微波功率400%、400%及500%條件下，經過300秒的退火時間，分別製作出具最佳電性之摻雜析離蕭特基奈米線電晶體。藉由和傳統快速熱退火技術所製作出的元件結果比較，得以驗證，利用微波退火之金屬汲/源極奈米線元件，除具低溫製程之優勢外，並有相對較佳的電特性，極利於應用在未來三維元件的製程製作上。

The thermal annealing process has a key function in determining the current-voltage characteristics of Schottky barrier nanowire transistors and associated Schottky barrier heights. Using low-temperature microwave annealing, this dissertation explores the fabrication and analysis of intrinsic and dopant segregated Schottky barrier nanowire transistors. Effects of microwave annealing on metals silicidation as well as dopants segregation are examined by comparing with those using rapid thermal annealing.
In this dissertation, three metals, nickel, ytterbium, and titanium, are considered as examples to explore their silicidation and segregation. Hard-mask sidewall oxide spacer is employed to fabricate the nanowire structure without any advanced lithography. The minimum microwave power of 80%, 200%, and 500% with processing time of 300 sec can be used to form the nickel, ytterbium, and titanium silicide to minimize the thermal energy while retaining sufficient activation and silicidation. For optimized characteristics, the microwave power of 400%, 400%, and 500% can be utilized to fabricate the Schottky barrier nanowire transistors. Experimental results show that the microwave annealing produce better electrical characteristics of Schottky barrier nanowire transistors, serving as a promising approach for future 3D integration of CMOS technologies.

誌謝 i
論文摘要 ii
Abstract iii
目次 iv
圖目次 vi
表目次 viii
中英文名詞對照 ix
第一章 序論 1 1
1.1 金屬矽化物 2
1.2 微波退火 3
1.3 蕭特基奈米線電晶體 7
1.4 摻雜析離蕭特基奈米線電晶體 8
1.5 無接面奈米線電晶體 9
1.6 論文架構 10
第二章 微波退火金屬矽化物之接面研製 15
2.1 微波加熱製程 15
2.2 微波退火矽化物薄膜分析 17
2.3 微波退火矽化物接面摻雜活化 20
第三章 微波退火摻雜活化之奈米線電晶體 39
3.1 奈米線電晶體之製作流程 39
3.2 摻雜活化之奈米線電晶體之特性分析 41
第四章 微波退火矽化物之蕭特基奈米線電晶體 48
4.1 蕭特基奈米線電晶體之製作流程 48
4.2 蕭特基奈米線電晶體之特性分析 49
4.3 摻雜析離蕭特基奈米線電晶體之特性分析 53
第五章 具矽化鎳源/汲極之無接面奈米線電晶體 74
5.1 微波退火低阻值矽化鎳 74
5.2 無接面奈米線電晶體之特性分析 76
第六章 結論 84
參考文獻 86

圖1-1： 微波退火發展應用 11
圖1-2： 蕭特基雙極性傳導能帶示意圖 12
圖1-3： 摻雜析離蕭特基電晶體之電性示意圖 13
圖1-4： 摻雜析離電晶體之影響因素示意圖 14
圖2-1： 微波退火加熱製程之 (A) 基本設置和 (A) 溫度量測示意圖 22
圖2-2： (A) 不同微波功率加熱時間固定為300S和 (B) 不同加熱時間微波功率固定為2P之溫度對時間特性圖 23
圖2-3： 矽化鎳、矽化鐿和矽化鈦薄膜之製作流程 24
圖2-4： 微波退火和快速熱退火 (A) 矽化鎳 (B) 矽化鐿 (C) 矽化鐿和 (D) 矽化鈦之XRD分析 26
圖2-5： (A) 快速熱退火和 (B) 微波退火矽化鎳、矽化鐿和矽化鈦薄膜之片電阻 27
圖2-6： 微波退火 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦之EDS分析 29
圖2-7： 微波退火 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦之TEM剖面圖 31
圖2-8： 金屬矽化物接面之製作流程 32
圖2-9： 微波退火 (A) 矽化鎳和 (B) 矽化鐿接面電流電壓特性圖 33
圖2-10： 磷和硼摻雜佈植矽化鐿接面之製作流程 34
圖2-11： 經微波退火活化之 (A) 磷和 (B) 硼摻雜佈植矽化鐿接面電流電壓之特性圖 35
圖2-12： 矽化鐿接面製作流程: (A) IBS和 (B) ITM 36
圖2-13： 矽化鐿接面電流電壓特性圖: (A) IBS和 (B) ITM 37
圖3-1： 奈米線電晶體之關鍵製作流程 (A)-(D) 42
圖3-2： 奈米線電晶體之 (A) 上視圖和 (B) 剖面圖 43
圖3-3： 垂直式堆疊奈米線電晶體之關鍵製作流程 (A)-(D) 44
圖3-4： 垂直式堆疊奈米線電晶體之TEM剖面圖 45
圖3-5： 奈米線電晶體之 (A) P型和 (B) N型 46
圖3-6： 垂直式堆疊和無垂直式堆疊奈米線電晶體之電流電壓曲線比較圖 47
圖4-1： 蕭特基奈米線電晶體之 (A) 主要結構示意圖和 (B) TEM剖面圖 58
圖4-2： 不同快速熱退火溫度之 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦蕭特基奈米線電晶體電流電壓曲線圖 61
圖4-3： 不同微波退火功率之 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦蕭特基奈米線電晶體電流電壓曲線圖 63
圖4-4： 最佳化 (A) 快速熱退火和 (B) 微波退火金屬矽化物蕭特基奈米線電晶體電流電壓曲線比較圖 64
圖4-5： 經不同溫度快速熱退火之摻雜析離 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦奈米線電晶體電流電壓曲線 66
圖4-6： 經不同微波功率退火之摻雜析離 (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦奈米線電晶體電流電壓曲線 68
圖4-7： 最佳化 (A) 快速熱退火和 (B) 微波退火摻雜析離金屬矽化物奈米線電晶體之電流電壓曲線比較圖 69
圖4-8： 微波退火和快速熱退火之摻雜析離金屬矽化物奈米線電晶體電流電壓曲線比較圖: (A) 矽化鎳 (B) 矽化鐿和 (C) 矽化鈦 71
圖5-1： 無接面奈米線電晶體之 (A) 主要結構示意圖和 (B) TEM剖面圖 78
圖5-2： 微波退火矽化鎳之XRD分析 79
圖5-3： 矽化鎳源/汲極和無矽化鎳源/汲極無接面奈米線電晶體之輸出特性曲線比較圖 80
圖5-4： 矽化鎳源/汲極和無矽化鎳源/汲極無接面奈米線電晶體之電流電壓曲線和
場效應遷移率比較圖 81
圖5-5 浮體基體效應之能帶示意圖 (A 無矽化鎳源/汲極和 (B) 矽化鎳源/汲極 82

表2-1： 微波退火溫度關係表 38
表4-1： 最佳化 (A) 快速熱退火和 (B) 微波退火蕭特基奈米線電晶體比較表 72
表4-2： 最佳化 (A) 快速熱退火和 (B) 微波退火摻雜析離蕭特基奈米線電晶體比較表 73
表5-1： 多閘極奈米線電晶體之電性比較表 83

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