臺灣博碩士論文加值系統

這篇論文主要是在呈獻出以軟硬體協同設計的方式時實現high efficiency advanced-audio-coding (HE-AAC) 的音訊解碼器， 基於我們複雜度的分析我們可以把這個音訊系統切個成兩個部分. 我們的軟體實現的部分為bitstream parser 和 低運算複雜度的部分， 其他高運算複雜度的地方以硬體實現，我們設計硬體的部分是以VLSI 的IP 方式呈現，在我們決定要以硬體方式實作出來的四個模組。其中IMDCT, analysis quadrature mirror filterbank (AQMF), synthesis quadrature mirror filterbank (SQMF).　這三個模組是以拆解成radix-2 FFT的方式去實現。在我們的設計之中，我們的IP有包上BUS的Wrapper和一些系統層級的實現方式. 我們以TSMC090 的製程去實現我們的設計. 我們的設計約為150K的gate count. 另外我們的IP以1.75MHz極低的運行時脈實現. 所以我們的功率消耗可以低至 7.69mw. 之後我們更進一部的將我們的IP 移植到ARM base 的開發板上可以達到即時的音樂播放.　當在ARM 系統的平台上，使用我們的IP 時可以保留ARM processor 約91.26% 的運算負載。

This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. Based on our computation analysis, the decoder system is partitioned into software part and hardware part respectively. We allocate the lower complexity part and bitstream parser with the software solution, and the higher complexity part with the hardware solution. We design the hardware part as an intellectual property (IP) in VLSI design domain. As in this dedicated hardware, four units are developed to cope with the IMDCT, analysis quadrature mirror filterbank (AQMF), synthesis quadrature mirror filterbank (SQMF). For these versatile transformation functi ons, the common radix-2 FFT is decomposed to manipulate it. In an overall system, IP-based implementation is constructed including the wrapper design and some system-level implementation. This design is using TSMC 90 nm library with about 150K gates. Alternatively it can execute at a very low operation frequency with 1.75 MHz. Besides, the power consumption is only 7.69 mW. We further port our design on an ARM Integrator platform to make a real playable system. Over 91.26% ARM performance loading can be saved and substituted by this HE-AAC intelligent property (IP).

摘要 i
Abstract i
Table of Contents iii
List of Figures v
List of Tables vi
Chapter 1 Introduction 1
Chapter 2 Analysis and Design Strategy…………………………………………4
2.1 Analysis 4
2.2 Design Strategy 7
2.2.1. Fast Algorithms 8
2.2.2. Formula Simplification 14
2.2.3. Improve Memory Access Order 15
2.2.4. Low Power Consumption Design 16
Chapter 3 Hardware struction we purposed 18
3.1 Stage1 19
3.2 Stage2 20
3.3 Stage3 22
3.4 Stage4 26
Chapter 4 Architecture of proposed design 28
4.1 Communction Between our ASIC and Processor 29
4.2 Pipeline Timing Char 31
Chapter 5 Experimental Result 32
5.1 Cell base 32
5.1.1. Resources use by Cell Base 32
5.1.2. Power Consumption Optimization 34
5.1.3. Power Consumption Comparison (ASIC with ARM processor) 36
5.2 SOPC platform 38
5.2.1. Platform Equipment 38
5.2.2. SOPC Structure of Proposed Design 39
Chapter 6 Conclusion 41
References 43

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