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研究生:劉翰穎
研究生(外文):LIU HAN-YING
論文名稱:應用於USB 3.1之展頻時脈產生器設計
論文名稱(外文):Design of Spread-Spectrum Clock Generator for USB 3.1 Application
指導教授:羅有龍
指導教授(外文):LO YU-LUNG
學位類別:碩士
校院名稱:國立高雄師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:中文
論文頁數:49
中文關鍵詞:展頻時脈產生器鎖相迴路
外文關鍵詞:spread spectrum clock generatorphase lock loop
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近年來,IC產業逐漸朝向單晶片系統設計發展,隨著複雜度的增加以及製程的快速演進,在系統中時脈產生器所扮演的腳色日益重要。隨著時脈持續上升,時脈訊號運作過程中向外輻射的能量,進而影響其他的電子產品,導致系統產生錯誤動作,對一個高速的傳輸系統其電磁干擾所造成的問題也日漸嚴重。
本論文利用基本的鎖相迴路搭配相位攪拌器與多模數頻率除頻器做為其控制單元,並將數位電路利用Cell-Based design flow合成,提出一個可控式展頻範圍的展頻時脈產生器,完成一個操作於5 GHz應用於USB 3.1 之展頻時脈產生器。
此展頻時脈產生器利用台積電 90nm 標準CMOS 製程,操作頻率為5 GHz 並透過外部腳位控制其展頻範圍5000/2500 ppm,並用一個頻率33 KHz的三角波來控制調變頻率。在未展頻時,其鎖相迴路的峰對峰抖動(peak-to-peak Jitter)為4.19 ps,在展頻的電磁干擾的壓抑約為17 dB。1.0 V電壓操作下功率消耗為 12.54 mW,整體核心面積為0.126 mm2

In recent years, rapid growth of portable electronic devices has led to a trend of system-on-a-chip (SoC). Due to SoC complexity increases and process comes soon, the clock generator is becoming an important component in high speed communication system. As the clock frequency becomes faster, the electromagnetic interference (EMI) induced by the clock generator will affect the other equipment.
In this thesis, design and implementation of adjustable range spread-spectrum clock generator for USB 3.1 Application is proposed. And use Cell-Based design flow to compile digital circuit. This design will use TSMC 90nm CMOS technology, and the operation frequency is 5 GHz, and spread spectrum range can be control 2500 ppm or 5000 ppm by output pin with a 33 KHz triangular waveform. The peak-to-peak jitter of phase lock loop clock is 4.19 ps. The EMI reduction is 17 dB with normal frequency spread modulation from 5 GHz to 4.975 GHz. The core area is 0.126 mm2. The power is 12.54 mW under 1.0-V supply voltage.

目錄
致謝 I
中文摘要 II
ABSTRACT III
目錄 IV
表目錄 VII
圖目錄 1
第一章 緒論 1
1.1背景簡介 1
1.2研究動機 2
1.3可能遭遇之困難 3
1.3.1相位切割誤差的問題 3
1.3.2量測雜訊的問題 3
1.3.3 Cell-Based Design APR的問題 4
1.3.4 製程、電壓及溫度變異的問題 4
1.3.5 高頻量測的問題 4
1.4研究方法與步驟 5
1.5論文架構 7
第二章 展頻時脈產生器概論 8
2.1展頻時脈產生器簡介 8
2.2展頻時脈產生器 10
2.2.1以延遲線為基礎之展頻時脈產生器 10
2.2.2以控制數位控制振盪器輸出之展頻時脈產生器 11
2.2.3以ΣΔ調變搭配多模數除頻器之展頻時脈產生器 12
2.2.4以輸入頻率調變技術為基礎之展頻時脈產生器 13
2.2.5以調變振盪器輸入電壓之展頻時脈產生器 14
2.2.6以調變振盪器輸出相位之展頻時脈產生器 15
2.2.7以多相位補償技術調變之展頻時脈產生器 16
2.3預計論文規格 17
第三章 應用於USB 3.1展頻時脈產生器 19
3.1應用於USB 3.1之鎖相迴路架構 20
3.1.1相位頻率偵測器(Phase Frequency Detector, PFD) 21
3.1.2充電泵(Charge Pump, CP) 21
3.1.3迴路濾波器(Loop Filter, LP) 22
3.1.4電壓控制振盪器(Voltage Controlled Oscillator, VCO) 24
3.1.5差動轉單端電路(Dual to Single) 26
3.2應用於USB 3.1之展頻控制器架構 27
3.2.1多模數除頻器(Multi-Mode Divider) 28
3.2.2相位補償單元(Phase Compensation Unit) 29
3.2.3三角波形產生器 (Address Profile) 33
第四章 展頻時脈產生器電路佈局與模擬結果 34
4.1展頻時脈產生器之電路佈局 34
4.1.1Pin Assignments 34
4.1.2晶片佈局圖 35
4.2展頻時脈產生器之系統模擬 36
4.3展頻時脈產生器之模擬結果 37
4.3.1相位頻率偵測器 37
4.3.2電壓控制振盪器 38
4.3.3相位補償單元 38
4.3.4三角波形產生器 39
4.3.5展頻時脈產生器整體模擬 40
4.4展頻時脈產生器之量測考量 43
第五章 結論與未來展望 46
5.1結論 46
5.2未來展望 46
參考文獻 47


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