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研究生:姚志杰
研究生(外文):Yao, Chih Chieh
論文名稱:在0.18μm標準製程下利用環震盪器設計並實現200M-1.6GHz低電壓敏感度的鎖相迴路
論文名稱(外文):Design and implementation of a 200M-1.6GHz PLL using a CMOS ring oscillator with low supply sensitivity in 0.18μm CMOS technology
指導教授:謝秉璇
指導教授(外文):Hsieh, Ping Hsuan
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:61
中文關鍵詞:低電源敏感度CMOS環震盪器鎖相迴路寬可調範圍
外文關鍵詞:low supply sensitivityCMOS ring oscillatorphase-locked loopwide tuning range
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鎖相迴路在時脈的產生與同步方面有著非常多的應用, 其時脈的品質對系統的效能有決定性的因素. 在這個SoC時代, 越來越多模組整合進同一顆晶片, 從電源來的雜訊就越來越大且其效果也越來越顯著. 目前已有很多作品去探討電源雜訊如何使系統的效能變低落, 也提出了一些改善的方法[4], [7], [8],[10]。

在這篇著作裡, 我們利用寬可調範圍200MHz到1.6GHz的環震盪器來設計並實現鎖相迴路. 此外, 我們因為current-starved架構有著滿幅震盪的特性, 所以我們挑選此做為延遲單位, 雖然環震盪器比LC震盪器較受電源所影響. 在這設計中, 我們在不同的操作頻率下選擇適當的電流鏡比例以達到訊號擺幅和充電電流的最適當平衡. 而藉此可在所有可調範圍下達成低電源敏感度的特性.

我們量測到的震盪器在其可調範圍內電源敏感度由-0.9%/%到1%/%. 而其在500MHz到1.2GHz中有很接近零的電源敏感度. 在給10mV, 20MHz的電源雜訊時, 此鎖相迴路的峰對峰絕對擾動小於20%的震盪週期, 而其峰對峰的週期擾動小於4%的震盪週期. 整體鎖相迴路在最高頻1.6GHz時需要36.17mW的功率消耗.

Phase-locked loops are widely used in many applications for clock
generation and synchronizations. The signal’s timing quality is
of critical importance to the system’s performance. As more and
more modules are integrated into the same chip in SoC era, the noise on the supply rails becomes larger and more significant.
Many prior works have investigated the performance degradation due to supply noise and proposed techniques for improvement[4], [7], [8], [10].
In this work, we have designed and implemented a PLL using a CMOS ring oscillator for its wide tuning range from 200 MHz to 1.6 GHz. Furthermore, current-starved structure is used for delay cells for its rail-to-rail characteristics. However, ring oscillators are more susceptible to supply noise than the LC counterpart. In
this design, the current mirror ratio is changed according to the operating frequency for optimal balance between the signal swing and charging current. This leads to low supply sensitivity over the tuning range.
The measured supply sensitivity is from
Contents ii
List of Tables iv
List of Figures v
1 Introduction 1
1.1 General Background Information . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Overview . . . . . . . . . . . . . . . . . 2
2 Noise Effect on PLL Performance 4
2.1 Internal Noise . . . . . . . . . . . . . . . . . . 5
2.1.1 PFD’s Noise . . . .. . . . . . . . . . . . . . . 5
2.1.2 Charge Pump’s Noise . . . . . . .. . . . . . . . 6
2.1.3 Loop Filter’s Noise . .. . . . . . . . . . . . . 6
2.1.4 Oscillator’s Noise . . . . . . . . . . . . . . . 7
2.1.5 Divider’s Noise . . . . . .. . . . . . . . . . . 9
2.2 External Noise . . . . . . . . . . . . . . . . . . 9
2.2.1 Loop Filter . . . . . . . . . . . . . . . . . . 9
2.2.2 Oscillator . . . . . . . . . . . . . . . . . . . 10

2.3 Noise Effect on PLL’s Performance . . . . . . . . 11
3 Voltage-Controlled Ring Oscillator 14
3.1 Introduction of Ring Oscillator . . . . . . . . . 14
3.1.1 Supply Sensitivity of Oscillator . . . . . . . . 16
3.2 Ring Oscillator with Low Supply Sensitivity. . . . 17
3.3 Dynamic Supply Sensitivity . . . . . . . . . . . . 23
3.4 Layout and Simulation Results . . . . . . . . . . 26
4 Implementation of Phase-Locked Loop 30
4.1 Parameters of PLL. . . . . . . . . . . . . . . . . 31
4.2 Phase Frequency Detector . . . . . . . . . . . . . 34
4.3 Charge Pump . . . . . . . . . . . . . . . . . . . 36
4.4 Loop Filter. . . . . . . . . . . . . . . . . . . . 41
4.5 Divider. . . . . . . . . . . . . . . . . . . . . . 45
4.6 Closed-Loop Simulation Results . . . . . . . . . . 46
5 Measurement Results 49
5.1 Chip Photo . . . . . . . . . . . . . . . . . . . . 49
5.2 PCB Board . . . . . . . . . . . . . . . . . . . . 51
5.3 Testing Method . . . . . . . . . . . . . . . . . . 53
5.4 Oscillator Measurement Results . . . . . . . . . . 54
5.5 Whole Loop’s Measurement Results . . . . . . . . . 56
6 Conclusion 59
Bibliography 60
[1] F. Herzel, B. Razavi, ”A Study of Oscillator Jitter Due to Supply and Substrate
Noise.” IEEE Circuits and Systems Society, vol. 46, no.1, pp. 56–62, Jan. 1999.

[2] X. Ge, M. Arcak, K.N. Salama, ”Nonlinear analysis of ring oscillator circuits.”
American Control Conference (ACC), pp. 1772–1776, Jan. 2010.

[3] B. Razavi, ”A study of phase noise in CMOS oscillators.” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331–343, Mar. 1996.

[4] P. Hsieh, J. Maxey, C.-K. K. Yang, ”Minimizing the Supply Sensitivity of
a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages.” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2488–2495, Sept. 2009.

[5] E. Soleiman, Kamarei, Mahmoud, ”New low current mismatch and wide output dynamic range charge pump.” Electrical Engineering (ICEE), pp. 1–5, May 2011.

[6] J.G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques." IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, Sept. 1996.

[7] T. Wu, K. Mayaram, U. Moon, ”An On-Chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 775–783, Sept. 2007.

[8] C. Lai, M. Shen, Y. Wu, K. Huang, P. Huang, ”A 0.24 to 2.4 GHz phaselocked loop with low supply sensitivity in 0.18-μm CMOS.” Circuits and Systems (ISCAS), pp. 981–984, 2011.

[9] S. Kao, S. Liu, ”A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. ” Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 592–602, 2011.

[10] M. Mansuri, C.-K. K. Yang,”A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation.” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, 2003.

[11] J. Lee, B. Kim, ”A low-noise fast-lock phase-locked loop with adaptive bandwidth control.” IEEE J. Solid-State Circuits , vol. 35, no. 8, pp. 1137–1145, Aug. 2000.

[12] E. Alon, J. Kim, S. Pamarti, K. Chang, M. Horowitz, ”Replica compensated linear regulators for supply-regulated phase-locked loops.” IEEE J. Solid-State Circuits , vol. 41, no. 2, pp. 413–424, Feb. 2006.
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