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研究生:許俊琛
研究生(外文):Chun-Chen Hsu
論文名稱:可重定目標且高效能之動態二元碼轉譯器框架系統
論文名稱(外文):Retargetable and Effi cient Dynamic Binary Translation Framework
指導教授:劉邦鋒
指導教授(外文):Pangfeng Liu
口試委員:郭大維楊佳玲徐慰中羅習五
口試委員(外文):Tei-Wei KuoChia-Lin YangWei-Chung HsuShi-Wu Lo
口試日期:2015-07-17
學位類別:博士
校院名稱:國立臺灣大學
系所名稱:資訊工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2015
畢業學年度:103
語文別:英文
論文頁數:96
中文關鍵詞:虛擬化二元碼翻譯
外文關鍵詞:binary translatorregion formationjust-in-time compilationQEMU
相關次數:
  • 被引用被引用:0
  • 點閱點閱:110
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
動態二元碼翻譯是虛擬化技術的核心技術因為它可用來加速指令集模擬。 對於動態二元碼翻譯器而言,其關鍵在於所翻譯的二元碼的質量, 以及是否可以在程式執行過程找到再優化增進效能的程
式區段。 在這論文中,我們呈現一個可重置的二元碼翻譯系統,此系統可產生高效能的動態二元碼翻譯器。 我們另提出二種執行熱區偵查方法來增加動態二元碼翻譯器的效能。 對一動態二元碼>
翻譯器而言,其翻譯的二元碼對於效能的影響甚為重要。故通常我們會對翻譯碼做手動優化。 然而這樣手動優化過的翻譯器是難以重置到另一系統,因為需要同樣的實作力氣來移植翻譯器到新的>
平台上。此論文首先提出一容易重置的二元碼翻譯系統,稱為 LLVM+QEMU (LnQ), 利用現有的編譯器技術來產生高效能的動態二元碼翻譯器。與 QEMU 相比, LnQ 在 ARM到 x86_64 及 x86 到 ARM
的動態二元碼翻譯器上於SPEC CINT2006中有高於2倍的效能表現。 此外,能否在程式執行過程中偵測出執行程式熱區也是影響效能的一關鍵因素。 在此論文中我們將指出現今熱區偵測方法不好
的地方, 亦即其所偵測的熱區會無法完全執行,如果這樣的熱區很多的話將會導至效能不佳。 我們首先提出測量此一弱點的方法來證明此弱點真的存在。進而我們再提出一改進此弱點的方法。 >
我們在此論文中提出一輕量級的熱區偵測技術稱為「Early-Exit Guided Region Formation (EEG)」。EEG 能持續地尋找出無法完全執行的熱區並將它與其他熱區合併來改進效能。 這方法對於
ARM 到 x86_64 的動態二元碼翻譯器能有效改進之前的方法約23%。對於x86_64 到 ARM的翻譯器約有11% 我們最後提出另一種以程序為單位的熱區偵測方法。並比較EEG與此方法的優劣。

Dynamic binary translation is one of the core technologies in virtualization to boost
the performace of instruction set architecture (ISA) simulation. The key factors
to the performace of dynamic binary translators are the quality of translated
code and the ability to detect hot regions at runtime.
This dissertation builds
a retargetable dynamic binary translator framework and provides two hot region
detection approaches to improve the performance of dynamic binary translators.
The quality of translated code is critical to the performance of a dynamic binary
translator, which implements the semantics of the
guest ISA instructions with the
host ISA
instructions, so the translated code is often carefully hand-optimized.
However a hand-optimized translator is not retargetabile because it takes tremen-
dous implementation e orts for software engineers to port it to a new host ISA.
This dissertation rst proposes an LLVM+QEMU (LnQ) framework for build-
ing high performance and retargetable binary translators with existing compiler
modules.
The goal of LnQ framework is to enable the process of building high
performance and retargetable dynamic binary translators with existing industry-
strength compiler optimization passes and code generation backends. Compared to
QEMU, the LnQ shows more than 2X speedup in CINT2006 for ARM-to-x86_64
and x86-to-ARM dynamic binary translators compared to QEMU.

Besides the quality of translated code, the ability to detect hot regions of guest
applications also determines the performance of dynamic binary translators. Most
dynamic binary translators target traces, i.e. frequently executed code paths, as
code regions to be translated and optimized. The
Next-Executing-Tail (NET) trace
formation method is an important example of such techniques. Many existing trace
formation schemes are variants of NET.
This dissertation examines the ine ciency of NET-like trace formation algorithms.
We found the formed traces may contain a large number of early exits that could
be branched out during the execution.
If this happens frequently, the program
execution will spend more time in the slow binary interpreter or in the unopti-
mized code regions than in the optimized traces in code cache. The bene t of the
trace optimization is thus lost. Traces with frequently taken early-exits are called
delinquent traces.
This dissertation proposes a light-weight region formation technique called
Early-
Exit Guided Region Formation (EEG) to improve the e ciency of traces.
It itera-
tively identi es and merges delinquent regions into larger code regions. It is shown
the EEG achieves 1.23X and 1.11X speedup in CINT2006 for ARM-to-x86_64 and
x86-to-ARM DBTs compared to NET.
This dissertation also studies the procedure-based dynamic binary translator that
detects hot procedures as its compilation (i.e. translation and optimization) unit.
We compare the performance of our EEG region formation algorithm with proce-
dure region.


口試 委員會 審定 書 i
Acknowledgements ii
誌謝 iv
Abstract v
摘要 vii
Contents viii
List of Figures xi
List of Tables xiii
1 Introduction 1
1.1 Retargetability of Dynamic Binary Translators . . . . . . . . . . . . 1
1.2 High Performance of Dynamic Binary Translators . . . . . . . . . . 3
1.2.1 Delinquent Trace . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Solution 1: Early-Exit Guided Region Formation . . . . . . 5
1.2.3 Solution 2: Trace-Guided Procedure-Based Region Formation 61.3
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . 9
2 The LLVM+QEMU (LnQ) Framework 10
2.1 LnQ: Design and Implementation . . . . . . . . . . . . . . . . . . . 10
2.1.1 LLVM Intermiediate Representation . . . . . . . . . . . . . . 11
2.1.2 IR Library and Instruction Description Table . . . . . . . . 12
2.1.3 LLVM IR Translator . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3.1 Register Mapping . . . . . . . . . . . . . . . . . . . 14
2.1.4 Emulation Module . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Runtime Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1 Block Linking . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Indirect Branch Target Caching . . . . . . . . . . . . . . . . 19
2.2.3 Shadow Stack . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.1 Experiment Settings . . . . . . . . . . . . . . . . . . . . . . 24
2.3.2 Performance of LnQ . . . . . . . . . . . . . . . . . . . . . . 24
2.3.3 Performance of LLVM Just-In-Time Compiler . . . . . . . . 25
2.3.3.1 Execution Time Spent in Code Cache . . . . . . . 26
2.3.3.2 Translation Overhead . . . . . . . . . . . . . . . . 27
2.3.4 Optimization Effects of Runtime Optimization . . . . . . . . 28
2.3.5 Slowdown of LnQ Compared to Native Run . . . . . . . . . 30
2.3.6 Performance of ARM-to-IA32 LnQ . . . . . . . . . . . . . . 32
2.3.7 Performance of IA32-to-ARM LnQ . . . . . . . . . . . . . . 32
2.4 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3 The Early-Exit Guided Code Region Formation 35
3.1 Region-Based Multi-threaded Dynamic Binary Translator . . . . . . 35
3.2 Early Exit Index and Early-Exit Guided Region Formation . . . . 38
3.2.1 Trace Formation Algorithm . . . . . . . . . . . . . . . . . . 38
3.2.2 Early Exit Index . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.3 Early-Exit Guided Region Formation . . . . . . . . . . . . . 40
3.2.4 Spill Index of a Region . . . . . . . . . . . . . . . . . . . . . 41
3.2.5 Region Versus Trace . . . . . . . . . . . . . . . . . . . . . . 42
3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.1 Performance Results of SPEC CPU2006 . . . . . . . . . . . 46
3.3.1.1 Performance of NET* . . . . . . . . . . . . . . . . 46
3.3.1.2 Performance of EEG Region Formation . . . . . . . 47
3.3.2 Early Exit Index . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.3 Performance Profiles of EEG . . . . . . . . . . . . . . . . . . 52
3.3.4 Effect of The Threshold of Spill Index . . . . . . . . . . . . 52
3.3.5 Statistics of Selected Traces and Regions . . . . . . . . . . . 54
3.3.6 Performance Comparison to Native Execution . . . . . . . . 58
3.3.7 Performance of EEG on IA32-to-ARM LnQ . . . . . . . . . 58
3.4 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4 Trace-Guided Procedure-Based Code Region Formation 61
4.1 Architecture of Dynamic Binary Translator . . . . . . . . . . . . . . 61
4.2 Procedure Compilation in Dynamic Binary Translation . . . . . . . 65
4.2.1 Call-Return Problem . . . . . . . . . . . . . . . . . . . . . . 66
4.2.2 Code/Data Distinction . . . . . . . . . . . . . . . . . . . . . 68
4.2.3 Targets of Indirect Branch . . . . . . . . . . . . . . . . . . . 69
4.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . 70
4.3.1 Experimental Environment and Settings . . . . . . . . . . . 70
4.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 72
4.3.2.1 Overview of the Performance . . . . . . . . . . . . 72
4.3.2.2 Detailed Performance of Procedure-Based DBT . . 73
4.4 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Related Works 76
5.1 Related Works of Dynamic Binary Translation (DBT) . . . . . . . . 76
5.1.1 QEMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.2 Retargetable Dynamic Binary Translators . . . . . . . . . . 77
5.1.3 Other Dynamic Binary Translators . . . . . . . . . . . . . . 79
5.2 Related Works of Region Formation . . . . . . . . . . . . . . . . . . 81
5.2.1 NET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.2 Most Recently Executed Tail2 . . . . . . . . . . . . . . . . . 81
5.2.3 NETPlus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2.4 Last-Executed Iteration (LEI) . . . . . . . . . . . . . . . . . 82
5.3 Related Works of Language Virtual Machines . . . . . . . . . . . . 83
5.3.1 Method-Based Language Virtual Machines . . . . . . . . . . 83
5.3.2 Trace-Based Language Virtual Machines . . . . . . . . . . . 85
6 Conclusion and Future Works 86
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.2 Future Research Direction . . . . . . . . . . . . . . . . . . . . . . . 88
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